The eMMC 5.1 controller is backward compatible to the eMMC 4.51 specification.
The enhancements to the eMMC controller for v4.51 to v5.1 include:
- HS400 mode operation with reference load and data strobe line (DQS) on the interface
- Production state awareness feature
- Field firmware update feature
- Sleep notification in power off notification
- Device health report feature
- Secure removal type feature
- Overshoot and undershoot
- Preamble and post-amble
- Command queuing
- Cache barrier and flushing report
- Replay protection memory block (RPMB) throughput improvement
- Write data size 8 KB (thirty two 512 B frames)
- Background operation control
- Secure write protection
- Host controller interface for command queuing as normative reference
- v5.1 in EXT_CSD_REV[192]
The performance of the eMMC unit matches the performance of the OSPI controller in its DDR mode (that is, 3200 Mb/s in 200 MHz DDR mode).