The following table lists the eMMC boot mode register settings.
| Register Name | Register Value | Description |
|---|---|---|
| PMC_IOP_SLCR | ||
| MIO_Bank1_Tristate |
0x0100_3FFF
|
Disable 3-state override |
| MIO_Bank1_Schmitt_En |
0x02FF_C000
|
Enable Schmitt trigger |
| EMMC_Cfg_Reg1 |
0x0000_1E50
|
|
| EMMC_Ctrl |
0x0000_0001
|
|
| EMMC_Cfg_Reg2 |
0x0000_1FFC
|
Generic enabled |
| CRP | ||
| PMCPLL_CTRL |
0x0002_4800
|
PMC PLL (PPLL) setup uses reset defaults (REF_CLK multiplied by72 (FBDIV) and divided by 4 (CLKOUTDIV) |
| RST_EMMC |
0x0000_0000
|
Deasserted |