XMPU Write Lock - XMPU Write Lock - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

All register writes to the protection unit must be done by a secure bus transaction as defined by TrustZone.

Once the XMPU LOCK [RegWrDis] register bit is set, access to the XMPU registers is disabled and can no longer be written to until after a POR reset. The only exception is a secure transaction can write to the interrupt status register (ISR).
Note: Regardless of the LOCK [RegWrDis] setting, the status registers are always writable by secure and non-secure transactions. All XMPU registers are only writable by a secure transaction. The registers are readable by secure or non-secure transactions.