Top-level Architecture
The Video Codec Unit (VCU2) core is capable of compressing and decompressing video streams simultaneously at resolutions of up to 3840 × 2160 pixels at 60 frames per second (4K UHD at 60 Hz). H.264/H.265/JPEG functionality is implemented as an embedded hard IP inside. The VCU2 contains both encode (compress) and decode (decompress) functions and is capable of simultaneous encode and decode compression that can be up to 8192 × 8192 with restrictions of limited frame rate. Decompression can be up to 4096 × 4096 with restrictions of limited frame rate.
VCU2 operation depends on built-VCUs RISC-V MCUs to service interrupts to coordinate data transfer. Each encoder and decoder is controlled by an MCU instance, and it uses a task list prepared in advance such that the response times are not in the execution critical path. Almost all control software is offloaded to an MCU.
VCU2 is suitable for applications including but not limited to video surveillance and video over IP connectivity. The applications supported include video conferencing, embedded vision, and biomedical instrumentation.
Feature Summary
Multi-standard encoding/decoding support, including:
- ISO MPEG-4 Part 10: Advanced Video Coding (AVC)/ITU H.264
- ISO MPEG-H Part 2: High Efficiency Video Coding (HEVC)/ITU H.265
- Supports various HEVC formats (see product guide for details)
- Supports various AVC formats (see product guide for details)
- Supports various JPEG formats (see product guide for details)
- Supports simultaneous encoding and decoding of up to 32 streams with a maximum aggregated bandwidth of 3840 x 2160 @ 60 fps
- Low latency rate control
- Flexible rate control: CBR, VBR, and Constant QP
- Supports simultaneous encoding and decoding up to 4K UHD resolution at 60 Hz of two video contents
- The encoder supports 8K UHD at reduced frame rate (~15 Hz) and the decoder supports up to 4K.
- Progressive support for H.264 and H.265; Interlaced support (sequence adaptive field-frame (SAFF) only)for H.265
- Video format support:
- Semi-planar formats, planar, and Y-only (monochrome):
- YUV420, YUV422 Semi-planar
- YUV444 planar
- Y400 only monochrome 8, 10 and 12-bit per color component
- Semi-planar formats, planar, and Y-only (monochrome):
Encoder Block Overview
The encoder engine is designed to process video streams using the HEVC (ISO/IEC 23008-2 high-efficiency Video Coding) and AVC (ISO/IEC 14496-10 Advanced Video Coding) standards (no JPEG encoding is supported). It provides support for these standards, including support for 8-bit, 10 and 12-bit color, Y only (monochrome), 4:2:0, 4:2:2, and 4:4:4 Chroma formats and up to 4K UHD at 60 Hz performance. Resolution up to 8K is supported with reduced framerate.
The encoder contains global registers, an interrupt controller, and a timer. The encoder is controlled by an integrated RISC-V 64-bit microcontroller (MCU) subsystem which handles the higher levels of encoder process. VCU applications running on the APU use the VCU control software library API to interact with the encoder microcontroller. The microcontroller firmware (MCU firmware) is not user modifiable. The encoder is a dual core IP, in the sense that each core allows for 4Kp30 encoding, while combining both cores allows 4Kp60 or 8Kp15 encoding. The encoder includes a cache for reducing DRAM bandwidth by reusing data fetched for motion estimation and other purposes.
The encoder cores and MCU use 128-bit AXI master interface with NoC NMU to move data into and out of external memory. The encoder IP provides a NSU interface to configure encoder parameters.
Decoder Block Overview
VCU comprises one instance of a single core decoder to process at the pixel level. The Decoder block can process video streams using the HEVC (ISO/IEC 23008-2 High Efficiency Video Coding), AVC (ISO/IEC 14496-10 Advanced Video Coding) and JPEG (ITU-standards). It provides support for these standards, including support for 8-bit, 10-bit, and 12-bit color depth, Y-only (monochrome), 4:2:0, 4:2:2, and 4:4:4 Chroma formats (up to 4K UHD at 60 Hz performance). It also contains global registers, an interrupt controller, and a timer.
The VCU decoder is controlled by a RISC-V 64-bit microcontroller (MCU) subsystem which handles the higher levels of decoder process. VCU applications running on the APU use the VCU control software library API to interact with the decoder microcontroller. The microcontroller firmware is not user modifiable.
The decoder includes control registers, a bridge unit, and a set of internal memories. The bridge unit manages the request arbitration, burst addresses, and burst lengths for all external memory accesses required by the decoder.
The decoder cores and MCU use a 128-bit AXI master interface with NoC NMU to move data into and out of external memory. The encoder IP provides 32-bit APB-S interface to configure decoder parameters.
Microcontroller Unit Overview
The encoder and decoder blocks each have a built-in RISC-V microcontroller unit (MCU) to handle interaction with the hardware blocks.
For more information on the Video CODEC Unit, see the Versal AI Edge Gen 2 H.264/H.265/JPEG Video Codec Unit 2 Solutions LogiCORE IP Product Guide (PG447) .
This document can be found in the AMD Versal™ AI Edge Series Gen 2 Documentation Early Access Site.