USB Register Overview - USB Register Overview - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)
Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The registers are classified into four groups. These registers are commonly used for various modes of operations (USB 2.0 host, device, and USB 3.2 host and device).

The base addresses of the controller is 0xEDEC0000

The register address map is shown in Table: Register Address Map. Further definition of these registers are listed in tables below.

  • xHCI host registers (Table: xHCI Host Registers)

  • Global registers (Table: Global Registers)

  • Device registers (Table: Device Registers)

Table 1. Register Address map
Address Index Register Type

0x0_0000 to 0x0_7FFF

  • 0 to CAPLENGTH – 1

  • CAPLENGTH to RTSOFF – 1

  • RTSOFF to DBOFF – 1

  • DBOFF to (xECP*4 – 1)

  • (xECP*4) to 0x0_7FFF

xHCI registers

  • xHCI capability registers

  • Host controller operational registers

  • Controller run time registers

  • Doorbell registers

  • xHCI extended capabilities
0x0_C100 to 0x0_C6FF Global registers
0x0_C700 to 0x0_CBFF Device registers
Table 2. xHCI Host Registers
Register Name Address Width Type Reset Value Description
CAPLENGTH 0xEDEC0000 32 ro x Capability Registers Length
HCSPARAMS1 0xEDEC0004 32 ro x Structural Parameters 1 Register
HCSPARAMS2 0xEDEC0008 32 ro x Structural Parameters 2 Register
HCSPARAMS3 0xEDEC000C 32 ro x Structural Parameters 3 Register
HCSPARAMS4 0xEDEC0010 32 ro 0x0118FFCD Capability Parameters 1 Register
DBOFF 0xEDEC0014 32 ro x Doorbell Offset Register
RTSOFF 0xEDEC0018 32 ro x Runtime Register Space Offset Register
HCCPARAMS2 0xEDEC001C 32 ro x

Host Controller Capability Parameters 2

For register definitions, see the xHCI specification
USBCMD 0xEDEC0030 32 mixed x USB Command Register
USBSTS 0xEDEC0034 32 mixed x USB Status Register Bit Definitions
PAGESIZE 0xEDEC0038 32 ro x Page Size Register Bit Definitions
DNCTRL 0xEDEC0044 32 mixed x Device Notification Register Bit Definitions
CRCR_LO 0xEDEC0048 32 mixed x CRCR_LO
CRCR_HI 0xEDEC004C 32 rw 0x00000000 CRCR_HI
DCBAAP_LO 0xEDEC0060 32 mixed x DCBAAP_LO
DCBAAP_HI 0xEDEC0064 32 rw 0x00000000 DCBAAP_HI
CONFIG 0xEDEC0068 32 mixed x Configure Register Bit Definitions
PORTSC_20 0xEDEC0430 32 mixed x

Port Status and Control Register Bit Definitions

The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted.

- PR

- ORC
PORTPMSC_20 0xEDEC0434 32 mixed x USB3 Port Power Management Status and Control Register Bit Definitions
PORTLI_20 0xEDEC0438 32 ro x Port Link Info Register
PORTHLPMC_20 0xEDEC043C 32 mixed x USB2 Port Hardware LPM Control Register Bit Definitions
PORTSC_30 0xEDEC0440 32 mixed x

Port Status and Control Register Bit Definitions

The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted.

- PR

- ORC

- WPR
PORTPMSC_30 0xEDEC0444 32 mixed x USB3 Port Power Management Status and Control Register Bit Definitions
PORTLI_30 0xEDEC0448 32 ro x Port Link Info Register
PORTHLPMC_30 0xEDEC044C 32 ro x USB2 Port Hardware LPM Control Register Bit Definitions
USBLEGSUP 0xEDEC0460 32 mixed x USBLEGSUP
USBLEGCTLSTS 0xEDEC0464 32 mixed x USBLEGCTLSTS
SUPTPRT2_DW0 0xEDEC0470 32 ro 0x02000402 SUPTPRT2_DW0
SUPTPRT2_DW1 0xEDEC0474 32 ro 0x20425355 SUPTPRT2_DW1
SUPTPRT2_DW2 0xEDEC0478 32 ro x xHCI Supported Protocol Capability_ Data Word 2
SUPTPRT2_DW3 0xEDEC047C 32 ro x SUPTPRT2_DW3
SUPTPRT2_DW0 0xEDEC0480 32 ro 0x03100802 Register SUPTPRT3_DW0
SUPTPRT3_DW1 0xEDEC0484 32 ro 0x20425355 Register SUPTPRT3_DW1
SUPTPRT3_DW2 0xEDEC0488 32 ro x SUPTPRT3_DW2
SUPTPRT3_DW3 0xEDEC048C 32 ro x SUPTPRT3_DW3
SUPTPRT3_DW4 0xEDEC0490 32 ro x SUPTPRT3_DW4
SUPTPRT3_DW5 0xEDEC0494 32 ro x SUPTPRT3_DW5
SUPTPRT3_DW6 0xEDEC0498 32 ro x SUPTPRT3_DW6
SUPTPRT3_DW7 0xEDEC049C 32 ro x SUPTPRT3_DW7
DCID 0xEDEC04A0 32 ro x DCID
DCDB 0xEDEC04A4 32 mixed x Register DCDB
DCERSTSZ 0xEDEC04A8 32 mixed x DCERSTSZ
RSVD0 0xEDEC04AC 32 ro x Reserved-0
DCERSTBA_LO 0xEDEC04B0 32 rw x DCERSTBA_LO
DCERSTBA_HI 0xEDEC04B4 32 rw 0x00000000 Register DCERSTBA_HI
DCERDP_LO 0xEDEC04B8 32 rw x DCERDP_LO
DCERDP_HI 0xEDEC04BC 32 rw 0x00000000 DCERDP_HI
DCCTRL 0xEDEC04C0 32 mixed x DCCTRL
DCST 0xEDEC04C4 32 ro x DCST
DCPORTSC 0xEDEC04C8 32 mixed x Register DCPORTSC
RSVD1 0xEDEC04CC 32 ro x Reserved-1
DCCP_LO 0xEDEC04D0 32 rw x DCCP_LO
DCCP_HI 0xEDEC04D4 32 rw 0x00000000 Register DCCP_HI
DCDDI1 0xEDEC04D8 32 rw x Register DCDDI1
DCDDI2 0xEDEC04DC 32 rw 0x00000000 Register DCDDI2
MFINDEX 0xEDEC1000 32 ro x Microframe Index Register Bit Definitions
RsvdZ 0xEDEC1004 32 ro x RsvdZ
IMAN_0 0xEDEC1020 32 mixed x Interrupter Management Register Bit Definitions. Instance 0 of an array of 4.
IMOD_0 0xEDEC1024 32 rw 0x00000FA0 Interrupter Moderation Register
ERSTSZ_0 0xEDEC1028 32 mixed x Event Ring Segment Table Size Register Bit. Instance 0 of an array of 4.
RsvdP_0 0xEDEC102C 32 ro x RsvdP. Instance 0 of an array of 4.
ERSTBA_LO_0 0xEDEC1030 32 mixed x ERSTBA_LO. Instance 0 of an array of 4.
ERSTBA_HI_0 0xEDEC1034 32 rw 0x00000000 ERSTBA_HI. Instance 0 of an array of 4.
ERDP_LO_0 0xEDEC1038 32 mixed 0x00000000 ERDP_LO. Instance 0 of an array of 4.
ERDP_HI_0 0xEDEC103C 32 rw 0x00000000 ERDP_HI Instance 0 of an array of 4.
IMAN_1 0xEDEC1040 32 mixed x Interrupter Management Register Bit Definitions
IMOD_1 0xEDEC1044 32 rw 0x00000FA0 Interrupter Moderation Register. Instance 1 of an array of 4.
ERSTSZ_1 0xEDEC1048 32 mixed x Event Ring Segment Table Size Register Bit Instance 1 of an array of 4.
RsvdP_1 0xEDEC104C 32 ro x RsvdP Instance 1 of an array of 4.
ERSTBA_LO_1 0xEDEC1050 32 mixed x ERSTBA_LO Instance 1 of an array of 4.
ERSTBA_HI_1 32 rw 0x00000000 ERSTBA_HI Instance 1 of an array of 4.
ERDP_LO_1 0xEDEC1058 32 mixed 0x00000000 ERDP_LO. Instance 1 of an array of 4.
ERDP_HI_1 0xEDEC105C 32 rw 0x00000000 ERDP_HI. Instance 1 of an array of 4.
IMAN_2 0xEDEC1060 32 mixed x Interrupter Management Register Bit Definitions. Instance 2 of an array of 4.
IMOD_2 0xEDEC1064 32 rw 0x00000FA0 Interrupter Moderation Register. Instance 2 of an array of 4.
ERSTSZ_2 0xEDEC1068 32 mixed x Event Ring Segment Table Size Register Bit. Instance 2 of an array of 4.
RsvdP_2 0xEDEC106C 32 ro x RsvdP Instance 2 of an array of 4.
ERSTBA_LO_2 0xEDEC1070 32 mixed x ERSTBA_LO Instance 2 of an array of 4.
ERSTBA_HI_2 0xEDEC1074 32 rw 0x00000000 ERSTBA_HI Instance 2 of an array of 4.
ERDP_LO_2 0xEDEC1078 32 mixed 0x00000000 ERDP_LO. Instance 2 of an array of 4.
ERDP_HI_2 0xEDEC107C 32 rw 0x00000000 ERDP_HI Instance 2 of an array of 4.
IMAN_3 0xEDEC1080 32 mixed x Interrupter Management Register Bit Definitions. Instance 3 of an array of 4.
IMOD_3 0xEDEC1084 32 rw 0x00000FA0 Interrupter Moderation Register. Instance 3 of an array of 4.
ERSTSZ_3 0xEDEC1088 32 mixed x Event Ring Segment Table Size Register Bit Definitions. Instance 3 of an array of 4.
RsvdP_3 0xEDEC108C 32 ro x RsvdP Instance 3 of an array of 4.
ERSTBA_LO_3 0xEDEC1090 32 mixed x ERSTBA_LO Instance 3 of an array of 4.
ERSTBA_HI_3 0xEDEC1094 32 rw 0x00000000 ERSTBA_HI Instance 3 of an array of 4.
ERDP_LO_3 0xEDEC1098 32 mixed 0x00000000 ERDP_LO Instance 3 of an array of 4
ERDP_HI_3 0xEDEC109C 32 rw 0x00000000 ERDP_HI Instance 3 of an array of 4.
DBn(n=0 to 127) 0xEDEC2000- 0xEDEC21FC 32 mixed x Doorbell Register Bit Field Instances 0 to 127, array of 128 registers.
Table 3. Global Registers
Register Name Address Width Type Reset Value Description
GSBUSCFG0 0xEDECC100 32 rw x Global SoC Bus Configuration Register 0
GSBUSCFG1 0xEDECC104 32 mixed x Global SoC Bus Configuration Register 1
GTXTHRCFG 0xEDECC108 32 rw x Global TX Threshold Control Register
GRXTHRCFG 0xEDECC10C 32 rw x Global RX Threshold Control Register
GCTL 0xEDECC110 32 mixed x

Global Core Control Register
GPMSTS 0xEDECC114 32 mixed x Global Power Management Status Register
GSTS 0xEDECC118 32 mixed x Global Status Register
GUCTL1 0xEDECC11C 32 mixed x Global User Control Register 1
USB31_IP_NAME 0xEDECC120 32 ro 0x33313130

IP NAME REGISTER

This is a read-only register that contains the SYNOPSYS IP NAME
GGPIO 0xEDECC124 32 mixed 0x00000000

Global General Purpose Input/Output Register

The application can use this register for general purpose input and output ports or for debugging.
GUID 0xEDECC128 32 rw 0x12345678

Global User ID Register

This is a read/write register containing the User ID. The power-on value for this register is specified as the User Identification Register. Power-on value during coreConsultant configuration (parameter DWC_USB31_USERID). This register can be used in the following ways:

- To store the version or revision of your system;

- To store hardware configurations that are outside the controller;

- As a scratch register.
GUCTL 0xEDECC12C 32 rw x

Global User Control Register

This register provides a few options for the software to control the controller behavior in Host mode.
GBUSERRADDRLO 0xEDECC130 32 ro 0x00000000

Global SoC Bus Error Address Register - Low

When the AHB or AXI requester bus returns an 'Error' response, the 'SoC Bus Error' is generated. In the Host mode, the host_system_err port indicates this condition. In addition, it is also indicated in the USBSTS.HSE field. In the Device mode, the GSTS.BusErrAddrVld field is the only indication of the SoC Bus Error.

Note for AXI configuration:

Due to the nature of AXI, it is possible that multiple AXI transactions are active at a time. The DWC_usb31 controller does not keep track of the start address of all outstanding transactions. Instead, it keeps track of the start address of the DMA transfer associated with all active transactions. It is this address that is reported in the GBUSERRADDR when a bus error occurs.

For example, if the DWC_usb31 controller initiates a DMA transfer to write 1k of packet data starting at buffer address 0xABCD0000, and this DMA is broken up into multiple 256B bursts on the AXI, then if a bus error occurs on any of these associated AXI transfers, the GBUSERRADDR reflects the DMA start address of 0xABCD0000 regardless of which AXI transaction received the error
GBUSERRADDRHI 0xEDECC134 32 ro 0x00000000

Global SoC Bus Error Address Register - High

When the AHB or AXI requester bus returns an 'Error' response, the 'SoC Bus Error' is generated. In the Host mode, the host_system_err port indicates this condition. In addition, it is also indicated in the USBSTS.HSE field. In the Device mode, the GSTS.BusErrAddrVld field is the only indication of the SoC Bus Error.

Note for AXI configuration:

Due to the nature of AXI, it is possible that multiple AXI transactions are active at a time. The DWC_usb31 controller does not keep track of the start address of all outstanding transactions. Instead, it keeps track of the start address of the DMA transfer associated with all active transactions. It is this address that is reported in the GBUSERRADDR when a bus error occurs.

For example, if the DWC_usb31 controller initiates a DMA transfer to write 1k of packet data starting at buffer address 0xABCD0000, and this DMA is broken up into multiple 256B bursts on the AXI, then if a bus error occurs on any of these associated AXI transfers, the GBUSERRADDR reflects the DMA start address of 0xABCD0000 regardless of which AXI transaction received the error
GPRTBIMAPLO 0xEDECC138 32 mixed 0x00000000 Global ESS Port to Bus Instance Mapping Register - Low
GPRTBIMAPHI 0xEDECC13C 32 ro x Global ESS Port to Bus Instance Mapping Register - High
GHWPARAMS0 0xEDECC140 32 ro 0x4020804A Global Hardware Parameters Register 0
GHWPARAMS1 0xEDECC144 32 ro 0x81092486 Global Hardware Parameters Register 1
GHWPARAMS2 0xEDECC148 32 ro 0x12345678 Global Hardware Parameters Register 2
GHWPARAMS3 0xEDECC14C 32 ro 0x88210086 Global Hardware Parameters Register 3
GHWPARAMS4 0xEDECC150 32 ro 0x48422020 Global Hardware Parameters Register 4
GHWPARAMS5 0xEDECC154 32 ro 0x643D0410 Global Hardware Parameters Register 5
GHWPARAMS6 0xEDECC158 32 ro 0x17C7803F Global Hardware Parameters Register 6
GHWPARAMS7 0xEDECC15C 32 ro 0x12C01D0A Global Hardware Parameters Register 7
GDBGFIFOSPACE 0xEDECC160 32 mixed x Global Debug Queue/FIFO Space Available Register
GBMUCTL 0xEDECC164 32 mixed x Global BMU Control Register
GBMUPSQWMARK 0xEDECC168 32 mixed 0x00008298 Global BMU Protocol Status Queue Water Mark Register
GDBGBMU 0xEDECC16C 32 ro 0x00000000 Global Debug BMU Register
GDBGLSPMUX 0xEDECC170 32 rw x

Global Debug LSP MUX Register in host mode

This register is for internal use only.
GDBGLSP 0xEDECC174 32 ro 0x00000000

Global Debug LSP Register

This register is for internal use only.
GDBGEPINFO0 0xEDECC178 32 ro 0x00000000

Global Debug Endpoint Information Register 0

This register is for internal use only.
GDBGEPINFO1 0xEDECC17C 32 ro 0x00800000

Global Debug Endpoint Information Register 1

This register is for internal use only.
GPRTBIMAP_HSLO 0xEDECC180 32 mixed 0x00000000 Global High-Speed Port to Bus Instance Mapping Register - Low
GPRTBIMAP_HSHI 0xEDECC184 32 ro x Global High-Speed Port to Bus Instance Mapping Register - High
GPRTBIMAP_FSLO 0xEDECC188 32 mixed 0x00000000 Global Full/Low-Speed Port to Bus Instance Mapping Register - Low
GPRTBIMAP_FSHI 0xEDECC18C 32 ro x Global Full/Low-Speed Port to Bus Instance Mapping Register - High
GHMSOCBWOR 0xEDECC190 32 rw 0x00000000 Global Host Mode SoC Bandwidth Override Register
USB31_VER_NUMBER 0xEDECC1A0 32 ro 0x3231302A

USB31 IP VERSION

- This register reflects the current corekit release number in ASCII format.
USB31_VER_TYPE 0xEDECC1A4 32 ro 0x67612A2A

USB31 IP VERSION TYPE

- This register reflects the current release type of the IP
GSYSBLKWINCTRL 0xEDECC1B0 32 rw x Global System Bus Blocking Window Control
GPCIEL1EXTLAT 0xEDECC1B4 32 mixed x Global PCIe L1 exit Latency Register
GUCTL2_USB4 0xEDECC1B8 32 rw 0x18044246 Global User Control Register 2 - USB4
GRXTHRCFG_USB4 0xEDECC1BC 32 rw x Global RX Threshold Control USB4 Register
GUSB2PHYCFG 0xEDECC200 32 mixed x Global USB2 PHY Configuration Register
GUSB3PIPECTL 0xEDECC2C0 32 mixed x Global USB 3.1 PIPE Control Register
GTXFIFOSIZ0 0xEDECC300 32 mixed x Global Transmit FIFO Size Register
GTXFIFOSIZ1 0xEDECC304 32 mixed x Register GTXFIFOSIZ 1
GTXFIFOSIZ2 0xEDECC308 32 mixed x Transmit FIFOn RAM Start Address
GTXFIFOSIZ3 0xEDECC30C 32 mixed x Register GTXFIFOSIZ 3
GTXFIFOSIZ4 0xEDECC310 32 mixed x Register GTXFIFOSIZ 4
GTXFIFOSIZ5 0xEDECC314 32 mixed x Register GTXFIFOSIZ 5
GTXFIFOSIZ6 0xEDECC318 32 mixed x Register GTXFIFOSIZ 6
GTXFIFOSIZ7 0xEDECC31C 32 mixed x Register GTXFIFOSIZ 7
GRXFIFOSIZ0 0xEDECC380 32 mixed x Global Receive FIFO Size Register
GRXFIFOSIZ1 0xEDECC384 32 mixed x Register
GRXFIFOSIZ2 0xEDECC388 32 mixed x Register
GRXFIFOSIZ3 0xEDECC38C 32 mixed x Register
GRXFIFOSIZ4 0xEDECC390 32 mixed x Register
GRXFIFOSIZ5 0xEDECC394 32 mixed x Register
GEVNTADRLO_0 0xEDECC400 32 rw 0x00000000 Global Event Buffer Address (Low) Register. Instance 0 of an array of 4.
GEVNTADRHI_0 0xEDECC404 32 rw 0x00000000 Global Event Buffer Address (High) Register. Instance 0 of an array of 4.
GEVNTSIZ_0 0xEDECC408 32 mixed x Global Event Buffer Size Register. Instance 0 of an array of 4.
GEVNTCOUNT_0 0xEDECC40C 32 mixed x Global Event Buffer Count Register. Instance 0 of an array of 4.
GEVNTADRLO_1 0xEDECC410 32 rw 0x00000000 Global Event Buffer Address (Low) Register. Instance 1 of an array of 4.
GEVNTADRHI_1 0xEDECC414 32 rw 0x00000000 Global Event Buffer Address (High) Register. Instance 1 of an array of 4.
GEVNTSIZ_1 0xEDECC418 32 mixed x Global Event Buffer Size Register. Instance 1 of an array of 4.
GEVNTCOUNT_1 0xEDECC41C 32 mixed x Global Event Buffer Count Register. Instance 1 of an array of 4.
GEVNTADRLO_2 0xEDECC420 32 rw 0x00000000 Global Event Buffer Address (Low) Register. Instance 2 of an array of 4.
GEVNTADRHI_2 0xEDECC424 32 rw 0x00000000 Global Event Buffer Address (High) Register. Instance 2 of an array of 4.
GEVNTSIZ_2 0xEDECC428 32 mixed x Global Event Buffer Size Register. Instance 2 of an array of 4.
GEVNTCOUNT_2 0xEDECC42C 32 mixed x Global Event Buffer Count Register. Instance 2 of an array of 4.
GEVNTADRLO_3 0xEDECC430 32 rw 0x00000000 Global Event Buffer Address (Low) Register. Instance 3 of an array of 4.
GEVNTADRHI_3 0xEDECC434 32 rw 0x00000000 Global Event Buffer Address (High) Register. Instance 3 of an array of 4.
GEVNTSIZ_3 0xEDECC438 32 mixed x Global Event Buffer Size Register. Instance 3 of an array of 4.
GEVNTCOUNT_3 0xEDECC43C 32 mixed x Global Event Buffer Count Register. Instance 3 of an array of 4.
GHWPARAMS8 0xEDECC600 32 ro 0x000017BF Global Hardware Parameters Register 8
GSMACCTL 0xEDECC604 32 rw x Global SMAC CONTROL REGISTER
GUCTL2 0xEDECC608 32 rw 0x18044246 Global User Control Register 2
GUCTL3 0xEDECC60C 32 rw x Global User Control Register 3
GTXFIFOPRIDEV 0xEDECC610 32 mixed x Global Device TXFIFO DMA Priority Register
GTXFIFOPRIHST 0xEDECC618 32 mixed x Global Host TXFIFO DMA Priority Register
GRXFIFOPRIHST 0xEDECC61C 32 mixed x Global Host RXFIFO DMA Priority Register
GFIFOPRIDBC 0xEDECC620 32 mixed x Global Host Debug Capability DMA Priority Register
GDMAHLRATIO 0xEDECC624 32 mixed x Global Host FIFO DMA High-Low Priority Ratio Register
GOSTDDMA_ASYNC 0xEDECC628 32 rw 0x18181218 Global Number of Async Outstanding DMA Register
GOSTDDMA_PRD 0xEDECC62C 32 rw 0x20201820 Global Number of Periodic Outstanding DMA Register
GFLADJ 0xEDECC630 32 rw x Global Frame Length Adjustment Register
GUCTL4 0xEDECC634 32 mixed x Global User Control Register 4
GUCTL5 0xEDECC638 32 rw x Global User Control Register 5
GUSB2RHBCTL 0xEDECC640 32 mixed x

Global USB2 Root Hub Control Register

In Host mode, per-port registers are implemented.
GUCTL6 0xEDECC680 32 rw 0x00000000 Global User Control Register 6
GUCTL7 0xEDECC684 32 rw 0x00000000 Global User Control Register 7
GUCTL8 0xEDECC688 32 rw 0x00000000 Global User Control Register 8
GUCTL9 0xEDECC68C 32 rw 0x00000000 Global User Control Register 9
GUCTL10 0xEDECC690 32 rw 0x00000000 Global User Control Register 10
GHWPARAMS9 0xEDECC6E0 32 ro x Global Hardware Parameters Register 9
Table 4. Device Registers
Register Name Address Width Type Reset Value Description
DCFG 0xEDECC700 32 rw x

Device Configuration Register.

This register configures the controller in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
DCTL 0xEDECC704 32 mixed x Device Control Register
DEVTEN 0xEDECC708 32 mixed x Device Event Enable Register
DSTS 0xEDECC70C 32 mixed x Device Status Register
DGCMDPAR 0xEDECC710 32 rw 0x00000000 Device Generic Command Parameter Register
DGCMD 0xEDECC714 32 mixed x Device Generic Command Register
DCTL1 0xEDECC718 32 rw x Device Control Register1.
DALEPENA 0xEDECC720 32 rw 0x00000000 Device Active USB Endpoint Enable Register.
DLDMENA 0xEDECC724 32 rw 0x00000000 Device LDM Request Control Register.
Rsvdn 0xEDECC728 to 0xEDECC7A4 32 ro x Reserved. Instance 0 to 31 from array of 32 registers
DEPCMDPAR2_0 0xEDECC800 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 0 of an array of 16.
DEPCMDPAR1_0 0xEDECC804 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 0 of an array of 16.
DEPCMDPAR0_0 0xEDECC808 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 0 of an array of 16.
DEPCMD_0 0xEDECC80C 32 rw x Device Physical Endpoint-n Command Register. Instance 0 of an array of 16.
DEPCMDPAR2_1 0xEDECC810 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 1 of an array of 16.
DEPCMDPAR1_1 0xEDECC814 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 1 of an array of 16.
DEPCMDPAR0_1 0xEDECC818 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 1 of an array of 16.
DEPCMD_1 0xEDECC81C 32 rw x Device Physical Endpoint-n Command Register. Instance 1 of an array of 16
DEPCMDPAR2_2 0xEDECC820 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 2 of an array of 16.
DEPCMDPAR1_2 0xEDECC824 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 2 of an array of 16.
DEPCMDPAR0_2 0xEDECC828 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 2 of an array of 16.
DEPCMD_2 0xEDECC82C 32 rw x Device Physical Endpoint-n Command Register. Instance 2 of an array of 16.
DEPCMDPAR2_3 0xEDECC830 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 3 of an array of 16.
DEPCMDPAR1_3 0xEDECC834 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 3 of an array of 16.
DEPCMDPAR0_3 0xEDECC838 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 3 of an array of 16.
DEPCMD_3 0xEDECC83C 32 rw x Device Physical Endpoint-n Command Register. Instance 3 of an array of 16.
DEPCMDPAR2_4 0xEDECC840 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 4 of an array of 16.
DEPCMDPAR1_4 0xEDECC844 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 4 of an array of 16.
DEPCMDPAR0_4 0xEDECC848 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 4 of an array of 16.
DEPCMD_4 0xEDECC84C 32 rw x Device Physical Endpoint-n Command Register. Instance 4 of an array of 16.
DEPCMDPAR2_5 0xEDECC850 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 5 of an array of 16.
DEPCMDPAR1_5 0xEDECC854 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 5 of an array of 16.
DEPCMDPAR0_5 0xEDECC858 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 5 of an array of 16.
DEPCMD_5 0xEDECC85C 32 rw x Device Physical Endpoint-n Command Register. Instance 5 of an array of 16.
DEPCMDPAR2_6 0xEDECC860 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 6 of an array of 16.
DEPCMDPAR1_6 0xEDECC864 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 6 of an array of 16.
DEPCMDPAR0_6 0xEDECC868 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 6 of an array of 16.
DEPCMD_6 0xEDECC86C 32 rw x Device Physical Endpoint-n Command Register. Instance 6 of an array of 16.
DEPCMDPAR2_7 0xEDECC870 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 7 of an array of 16.
DEPCMDPAR1_7 0xEDECC874 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 7 of an array of 16.
DEPCMDPAR0_7 0xEDECC878 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 7 of an array of 16.
DEPCMD_7 0xEDECC87C 32 rw x Device Physical Endpoint-n Command Register. Instance 7 of an array of 16
DEPCMDPAR2_8 0xEDECC880 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 8 of an array of 16.
DEPCMDPAR1_8 0xEDECC884 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 8 of an array of 16.
DEPCMDPAR0_8 0xEDECC888 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 8 of an array of 16.
DEPCMD_8 0xEDECC88C 32 rw x Device Physical Endpoint-n Command Register. Instance 8 of an array of 16.
DEPCMDPAR2_9 0xEDECC890 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 9 of an array of 16.
DEPCMDPAR1_9 0xEDECC894 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 9 of an array of 16.
DEPCMDPAR0_9 0xEDECC898 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 9 of an array of 16.
DEPCMD_9 0xEDECC89C 32 rw x Device Physical Endpoint-n Command Register. Instance 9 of an array of 16.
DEPCMDPAR2_10 0xEDECC8A0 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 10 of an array of 16.
DEPCMDPAR1_10 0xEDECC8A4 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 10 of an array of 16.
DEPCMDPAR0_10 0xEDECC8A8 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 10 of an array of 16.
DEPCMD_10 0xEDECC8AC 32 rw x Device Physical Endpoint-n Command Register. Instance 10 of an array of 16.
DEPCMDPAR2_11 0xEDECC8B0 32 rw 0x00000000

Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)

This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.

Instance 11 of an array of 16.
DEPCMDPAR1_11 0xEDECC8B4 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 11 of an array of 16.
DEPCMDPAR0_11 0xEDECC8B8 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 11 of an array of 16.
DEPCMD_11 0xEDECC8BC 32 rw x Device Physical Endpoint-n Command Register. Instance 11 of an array of 16.
DEPCMDPAR2_12 0xEDECC8C0 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 12 of an array of 16.
DEPCMDPAR1_12 0xEDECC8C4 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 12 of an array of 16.
DEPCMDPAR0_12 0xEDECC8C8 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 12 of an array of 16.
DEPCMD_12 0xEDECC8CC 32 rw x Device Physical Endpoint-n Command Register. Instance 12 of an array of 16.
DEPCMDPAR2_13 0xEDECC8D0 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 13 of an array of 16.
DEPCMDPAR1_13 0xEDECC8D4 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 13 of an array of 16.
DEPCMDPAR0_13 0xEDECC8D8 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 13 of an array of 16.
DEPCMD_13 0xEDECC8DC 32 rw x Device Physical Endpoint-n Command Register. Instance 13 of an array of 16.
DEPCMDPAR2_14 0xEDECC8E0 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 14 of an array of 16.
DEPCMDPAR1_14 0xEDECC8E4 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 14 of an array of 16.
DEPCMDPAR0_14 0xEDECC8E8 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 14 of an array of 16.
DEPCMD_14 0xEDECC8EC 32 rw x Device Physical Endpoint-n Command Register. Instance 14 of an array of 16.
DEPCMDPAR2_15 0xEDECC8F0 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n). Instance 15 of an array of 16.
DEPCMDPAR1_15 0xEDECC8F4 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 15 of an array of 16.
DEPCMDPAR0_15 0xEDECC8F8 32 rw 0x00000000 Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 15 of an array of 16.
DEPCMD_15 0xEDECC8FC 32 rw x Device Physical Endpoint-n Command Register. Instance 15 of an array of 16.
DEV_IMOD0 0xEDECCA00 32 rw 0x00000000 Device Interrupt Moderation Register (DEV_IMOD)
DEV_IMOD1 0xEDECCA04 32 rw 0x00000000 Device Interrupt Moderation Register (DEV_IMOD)
DEV_IMOD2 0xEDECCA08 32 rw 0x00000000 Device Interrupt Moderation Register (DEV_IMOD)
DEV_IMOD3 0xEDECCA0C 32 rw 0x00000000 Device Interrupt Moderation Register (DEV_IMOD)