The PS High-Speed Connectivity peripherals includes 1 channel USB 3.2 Gen 2x1 Dual Role Device (DRD) that supports the following speeds: SuperSpeed+ (SS+ at 10-Gb/s), SuperSpeed (SS at 5-Gb/s), High Speed (480-Mb/s), Full Speed (12-Mb/s) and Low Speed (1.5-Mb/s) operation modes. The DRD allows simultaneous transport of USB (up to 10 Gb/s) and DP 1.4 with HDCP 2.3 (up to 4K) traffic over a single USB Type-C connector. Type-C lane usage is set by configuring a mux whose output is attached to USB3 PHY. A Display Controller (DC) can send and receive stream data directly to/from the PL or can fetch video data from memory through a DMA engine. The DC is covered in a later section.
The USB 3.2 Gen 2x1 DRD controller will also support USB 2.0 functionality through a separate USB 2.0 PHY. The below table describes USB controller configurations.
| USB 3.2 Configuration | Description |
|---|---|
| USB 3.2 Device Controller | Enhanced SuperSpeed+, SuperSpeed, High-Speed, and Full-Speed |
| USB 3.2 Host Controller |
|
| USB 3.2 Static Dual-Role Device(DRD) Controller |
|
- One USB3.x DRD controller
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10 Gb/s IN and 10 Gb/s OUT bandwidth (interpacket delays and protocol overhead included)
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Doesn't supports on-the-go (OTG) mode of operation
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Provides simultaneous operation of the USB 2.0 and USB 3.2 interfaces (only in host mode)
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Up to 16 bidirectional endpoints, including control endpoint 0
- Multiple IN transfer support in SSP mode
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Software directly handles non-timing-critical and rarely occurring tasks, such as control transactions
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Flexible endpoint configuration allows a single area optimized configuration meeting multiple applications/USB set-configuration modes
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During core Consultant configuration, you can configure n number of endpoints, and software can then map the USB endpoint to an endpoint resource number, even if the USB endpoint numbers are not contiguous.
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Dynamic mappable TX FIFOs to support more TX-endpoints than the physical FIFOs
- Simultaneous IN and OUT transfer support
- Descriptor caching and data pre-fetching for predictable performance in high-latency system
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Hardware handles ERDY and burst and all data transfers
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Capability to set up multiple transfers without interrupting the host processor on every transfer
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Stream-based bulk endpoints with controller automatically initiating data movement
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Isochronous endpoints with isochronous data in data buffers or external hardware FIFOs
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The external buffer control (EBC) feature allows transfers to be setup in external FIFOs
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Flexible Descriptor with rich set of features to support buffer interrupt moderation, multiple transfers, isochronous, control, and scattered buffering support
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Multiple interrupt support – An endpoint interrupt can be mapped to a selected interrupt line during the endpoint configuration
Loopback Operation
The USB controller provides internal PIPE loopback and USB 3.2 external connector RX/TX loopback modes. The loopback testing can be software controlled or internal BIST based. The loopback mode is transparent to BIUM/BIUS, CSR, BMU, and LSP modules and mostly to PTL/MAC and Link modules. The PTL/MAC module emulates the Host/Device ACK functions, and the Link Layer provides the PIPE loop back support. This allows the loop back to follow the normal data transfer flow and test most of the controller and PHY logic as if they run normal data transfers. The below diagrams show the controller system level block diagram and main blocks.
The application layer (APP) is common for USB 2.0 and USB 3.2 operation. This has the Bus Interface, Buffer Management block, List Processor for scheduling, and Control and Status Register (CSR) functions.
The MAC layer has USB 2.0 and USB 3.2-specific MAC functions. It includes the PHY interface, the link layer, and the protocol layers.
In host mode, both USB 2.0 and USB 3.2 operations can be simultaneously active to concurrently support USB 2.0 and USB 3.2 devices. However, in device mode, because the controller connects as either a USB 2.0 device or a USB 3.2 device, only one of these operations is active at a given time.
In multi-port host mode, multiple instances of the PHY, Link, and MAC layers are instantiated. Buffer management also has separate RX and TX buffers for each bus instance.