The UFS host controller interface includes three signals mapped in the PMC MIO banks and a set of dedicated pins in bank 507. The PMC MIO bank pins include a UFS reset, UFS physical interface configuration clock input, and optional card detect input for removable UFS devices. See the MIO-at-a-Glance Tables section for PMC MIO pins. The dedicated bank includes pins for a differential input reference clock, transmit lanes, and receive lanes.
The AXI data widths between the LPD interconnect switch to the PMC IOP switch via the PMC switch is 128 bits wide. The AXI interface on the PMC IOP switch is 128 bits for the UFS host controller.
UFS Host Controller Interface Signals
The UFS host conrtoller interface signals are listed in the following table.
| Signal Name | Description | MIO-at-a-Glance Table Pin Name |
I/O |
|---|---|---|---|
| MIPI_REF_CLKP_507 MIPI_REF_CLKN_507 | UFS host controller differential reference clock input. A common
external clock source
1
shall supply the UFS host controller differential
inputs and UFS device REF_CLK input. If UFS is unused, tie low. |
– | Input |
| MIPI_RXDP0_507 MIPI_RXDN0_507 | UFS host controller upstream receive lane 0 differential input from
UFS device DOUT0_t/DOUT0_c. If UFS is unused, tie low or leave floating. |
– | Input |
| MIPI_RXDP1_507 MIPI_RXDN1_507 | UFS host controller upstream receive lane 1 differential input from
UFS device DOUT1_t/DOUT1_c. If UFS is unused, tie low or leave floating. |
– | Input |
| MIPI_TXDP0_507 MIPI_TXDN0_507 | UFS host controller downstream transmit lane 0 differential output
to UFS device DIN0_t/DIN0_c. If UFS is unused, leave floating. |
– | Output |
| MIPI_TXDP1_507 MIPI_TXDN1_507 | UFS host controller downstream transmit lane 1 differential output
to UFS device DIN1_t/DIN1_c. If UFS is unused, leave floating. |
– | Output |
| MIPI_RESREF_507 | UFS host controller physical interface connection for external
calibration reference resistor
1
. If UFS is unused, leave floating. |
– | – |
| VCC_MIPI_507 | UFS host controller physical interface digital power supply. 3 | – | – |
| VCCIO_MIPI_507 | UFS host controller physical interface analog power supply. 3 | – | – |
| UFS_CD_b | UFS host controller active-Low card detect input | CD 2 | Input |
| UFS_CFG_CLK | UFS host controller physical interface configuration input clock 1 | CFGCLK 2 | Input |
| UFS_RST_b | UFS host controller active-Low hardware reset output to UFS device RST_n | RST 2 | Output |
|
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