The low-latency, tightly-coupled memories (TCMs) provide predictable instruction execution and predictable data load/store timing for the RPU processors. TCM memory address space is not cached by the RPU processors.
Each RPU processor contains two 32 KB memory banks and one 64 KB memory bank that are accessed to the RPU processors via the TCM port interfaces, for a total of 128 KB per processor.
The parallel memory architecture of the RPUs allows concurrent accesses of all three banks by the CPU's load-store unit, instruction prefetch unit, and AXI destination port. Datapaths are 64-bits wide and are protected by ECC. Each CPU includes multiple datapaths to their TCMs.
- 64 KB TCM_A
- 32 KB TCM_B
- 32 KB TCM_C
TCMs are accessible after the processor is taken out of reset. The processor must be inactive (idle) or in the halt state to allow another processor to access the TCMs. The processors have direct connections to their TCMs for low-latency access and there are no protection units.
TCM Nomenclature
Usages
The TCMs can be used for any purpose, but are typically used as follows:
- TCM_A for interrupt or exception code for high speed, without cache miss delays
- TCM_B and TCM_C for data in process-intensive applications such as audio or video processing
System Memory-Mapped
In addition to the low-latency, local access path from the RPUs, the TCMs are memory-mapped on the interconnect and can be accessed by the PPU, APU, and other processors. However, these accesses are not low-latency:
- TCM address space starts at 0xEBA0_0000
System memory-mapped accesses must be done with 16B or 64B transfers on a 16B boundary.