Each controller generates two system interrupts.
- Wake-up interrupt
- Controller interrupt managed by three sets of register controls
- Normal interrupts, see the NORM_INTR_STS register
- DMA interrupts, see the ADMA_ERR_STS register
- Error interrupts, see the ERR_INTR_STS register
The enabled controller interrupts are OR'd together and assert the SD/eMMCx system interrupt. The wake-up interrupt is separate from the controller interrupts. All system interrupts are listed in the System Interrupts.