The hardware architecture includes a rich set of adaptable processing, acceleration hardware, and programmable logic that is configurable for connectivity. This enables customized, heterogeneous hardware solutions for a wide variety of applications across many markets. Each device incorporates a processing system with multiple Arm® based real-time and application processor CPU clusters. Each device also includes a platform management controller (PMC) and interfaces for standard I/O peripherals and flash memories for boot and general use. Features are added to provide high safety and reliability. These include ECC circuits, redundant processors, safety check registers, and more. These processors, peripherals, and other functionality are described in the technical reference manual.
The device also includes Arm TrustZone technology plus several types of other security related functionality. These are described in other documents that are available on the Security lounge.
All devices include LVCMOS and high-speed I/O channels for a mix of needs. All devices include a large array of programmable logic (PL) that includes configurable memories , DSPs, and logic blocks. The device includes a large, high-performance network on chip (NoC) interconnect to enable device-level subsystems to access the DDR memory controllers and other subsystems in the device. These features are introduced in the TRM and detailed in other documents.
In addition to these standard features, the hardware architecture includes device options to accelerate communications, processing power, and video/graphics. These are introduced in the TRM and detailed in other documents.
The TRM includes an overall introduction to the entire chip and details for the processing system and platform management controller. The TRM topics and a document list for the NoC, DDR memory, and device options are provided in Documentation.