The detection of single point faults is supported with these features:
- ECC protection for OCM, PPU RAM, PMC RAM, RPU L1 cache, and TCM memories
- Address decode error detection
- Separate RAMs for ECC syndrome and data
- 4:1 or greater interleaving of memory cells protected by ECC
- Hash validation of RCU ROM contents at every boot
- Lockstep and redundancy covers
Cortex-R52
processor
- Lockstep with physical and temporal diversity
- Redundant logic in critical control logic including the lockstep checkers
- PPU and RCU controllers are implemented with redundancy
- MicroBlaze™ triple modular redundancy (TMR) cores with physical diversity
- Triple redundant flip-flops for critical control bits such as security state
- XMPU and XPPU protect memory space
- Windowed watchdog timers in LPD and FPD