Most system interrupts are active-High, level-sensitive except:
- GEM wake on LAN (WOL) interrupt (rising clock, edge sensitive)
- PL interrupts (rising clock, edge sensitive)
PL Interrupt Pulse Width
The 16 interrupts from the PL are rising clock, edge sensitive. The minimum pulse must provide a width that is large enough for the GICs to catch. The pulse width must be at least two clock periods of the interrupt controller.
- PL_PS_Group0_[0:7] to LPD (RPU GIC)
- PL_PS_Group1_[0:7] to FPD (APU GIC)
Shorter interrupt pulse widths might not be detected. Avoid glitches and interrupt widths shorter than two GIC clock periods. The GICs are often driven with a 100 MHz clock frequency.