SWDT Block Diagram - SWDT Block Diagram - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The system watchdog timer block diagram is shown in the following figure.

Figure 1. System Watchdog Timer Block Diagram

I/O Signals

The I/O signals coming from the SWDT are shown the SWDT I/O Interface section.