SMID Summary Table - SMID Summary Table

SMID Summary Table - SMID Summary Table - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID

AM026

Release Date

2025-12-23

Revision

1.3 English

The following table lists the default system management IDs (SMID).

Table 1. System Management ID Summary Table
Host Name		Default SMID [9:0]	Notes and Configuration Registers
RPU Subsystem
RPU A core 0 RPU A core 1 RPU B core 0 RPU B core 1 RPU C core 0 RPU C core 1 RPU D core 0 RPU D core 1 RPU E core 0 RPU E core 1		`10_0000_0000` `10_0000_0001` `10_0000_0010` `10_0000_0011` `10_0000_0100` `10_0000_0101` `10_0000_0110` `10_0000_0111` `10_0000_1000` `10_0000_1001`	RPU interfaces to LPD OCM Switch
LPD_DMA_0	CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7	`10_0001_000x` `10_0001_001x` `10_0001_010x` `10_0001_011x` `10_0001_100x` `10_0001_101x` `10_0001_110x` `10_0001_111x`	LPD DMA controller 0; set bit [0] using the LPD_SLCR.LPD_DMA0_SMID_CFG register
LPD_DMA_1	CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7	`10_0001_000x` `10_0001_001x` `10_0001_010x` `10_0001_011x` `10_0001_100x` `10_0001_101x` `10_0001_110x` `10_0001_111x`	LPD DMA controller 0; set bit [0] using the LPD_SLCR.LPD_DMA1_SMID_CFG register
USB controller 0 USB controller 1		`10_0011_0000` `10_0011_0001`	USB 2.0 controllers;
GEM controller 0 GEM controller 1 GEM controller 2 GEM controller 3		`10_0011_0100` `10_0011_0101` `10_0011_0110` `10_0011_0111`	Gigabit Ethernet MAC controllers
DPC_DMA		`10_0011_1101`	Debug packet controller streaming DMA unit
ASU Subsystem
ASU RISC V		`10_0100_1100`	Application security unit (ASU) RISC processor registers
ASU DMA 0		`10_0100_1101`	ASU DMA controller 0
ASU DMA 1		`10_0100_1110`	ASU DMA controller 1
PMC Subsystem
JTAG DAP		`10_0100_0000`	JTAG Debug access port (DAP) controller
DPC		`10_0100_0001`	Debug packet controller
SD_DMA		`10_0100_0010`	SD v4.51 controller
eMMC_DMA		`10_0100_0011`	eMMC v5.1 controller
QSPI		`10_0100_0100`	Quad SPI flash memory controller
OSPI		`10_0100_0101`	Octal SPI flash memory controller
UFS		`10_0100_0110`	Universal flash storage controller
RCU processor		`10_0100_1000`	Runs RCU BootROM code
PPU processor		`10_0100_1001`	Runs PLM firmware
PMC_DMA0 PMC_DMA1		`10_0100_101010_0100_1011`	PMC DMA controller
APU Subsystem
Processor Cores APU A core 0 APU A core 1 APU B core 0 APU B core 1 APU C core 0 APU C core 1 APU D core 0 APU D core 1		`10_0110_0000` `10_0110_0001` `10_0110_1000` `10_0110_1001` `10_0111_0000` `10_0111_0001` `10_0111_1000` `10_0111_1001`	APU processor interfaces to the CMN interconnect
APU processor ACP interfaces: APU cluster A APU cluster B APU cluster C APU cluster D		`10_0110_0100` `10_0110_1100` `10_0111_0100` `10_0111_1100`	ACP interfaces to the PL
APU processor housekeeping interfaces: APU cluster A APU cluster B APU cluster C APU cluster D		`10_0110_0101` `10_0110_1101` `10_0111_0101` `10_0111_1101`
APU GIC		`10_0011_1110`	APU interrupt controller
CoreSight Debug		`10_0101_1001`	CoreSight
Integrated Device Options
MMI PCIe 0 MMI PCIe 1		`10_0101_0000` `10_0101_0001`
GPU 0 GPU 1 GPU 2 GPU 3 GPU 4 GPU 5 GPU 6 GPU 7 GPU 8 GPU 9		`10_0101_0100` `10_0101_0101` `10_0101_0110` `10_0101_0111` `10_0101_1000` `10_0101_1001` `10_0101_1010` `10_0101_1011` `10_0101_1100` `10_0101_1101`	GPUs
MMI_USB		`10_0000_1110`
MMI_DPC		`10_0011_1111`
MMI_DISPLAY		`10_0000_1111`
MMI_GEM		`10_0101_1110`