SMID Implementations - SMID Implementations - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The following table summarizes the SoC generations and SMID implementations.

Table 1. SMID Implementations
Device Generation SMID Override Capability
UltraScale+ MPSoC no no
Versal device yes no
Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 yes yes

Zynq UltraScale+ MPSoC to Versal Device Comparisons

In the AMD Zynq™ UltraScale+™ MPSoC, the ID was either a fixed 10-bit value such as USB, SD, etc., or a combination of a fixed value and a subset of the AXI ID.

The Versal device uses the SMID, which is a new type of device ID. The SMID replaces the Zynq UltraScale+ MPSoC ID. The SMID provides several advantages:

  • Flexibility
  • Scalability
  • ID assignment is not tied to the choice of PS input port
  • ID is unique regardless of the path it takes via hard/soft interconnect or NoC
  • ID is unique regardless of the physical location of the soft IP attachment to the NoC (that is, support for relocatable partial reconfiguration)
  • ID is preserved in cases of PL device virtualization/coherency (PL to NoC to PS to NoC to DDRMC)