SLCR Registers - SLCR Registers - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)
Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The UART system-level control registers (SLCR) include APB parity detection interrupts and MIO pin routing programming.

SLCR registers:

  • LPD_IOP_SLCR register module.
  • PMC_IOP_SLCR register module.
Table 1. UART System-Level APB Parity and MIO Pin Registers
Register Name Bit Field Access Type Description
LPD_IOP_SLCR APB parity error
PARITY_ISR

PARITY_IMR

PARITY_IER

PARITY_IDR

[perr_uart0_apb]
[perr_uart1_apb]

W1C, R
R
W
W

 Parity error detected on APB programming interface write data
LPD_IOP_SLCR MIO bank select
LPD_MIO_Sel

[UART0_SEL]
[UART1_SEL]

 RW Select between PMC and LPD MIO muxes
LPD_IOP_SLCR MIO pin select
MIO_PIN_0 through

MIO_PIN_25

[L0_SEL]
[L1_SEL]
[L2_SEL]
[L3_SEL]

 RW LPD mux MIO routing.

To select pins, refer to MIO-at-a-Glance Tables section.
PMC_IOP_SLCR MIO pin select
MIO_PIN_0 through

MIO_PIN_51

[L0_SEL]
[L1_SEL]
[L2_SEL]
[L3_SEL]

 RW PMC mux MIO routing.

To select pins, refer to MIO-at-a-Glance Tables section.