The programmable transaction routing and coherency controls are summarized in the following table.
| Transaction Host | Routing Control | AxCACHE Signal Control |
|---|---|---|
| OCM_ASILD | ||
| RPU0A processor | OCM_ASIL_D_CFG | Generated by the R5F processor |
| RPU1A processor | OCM_ASIL_D_CFG | Generated by the R5F processor |
| RPU0B processor | OCM_ASIL_D_CFG | Generated by the R5F processor |
| RPU1B processor | OCM_ASIL_D_CFG | Generated by the R5F processor |
| RPU0C processor | OCM_ASIL_D_CFG | Generated by the R5F processor |
| RPU1C processor | OCM_ASIL_D_CFG | Generated by the R5F processor |
| RPU0D processor | OCM_ASIL_D_CFG | Generated by the R5F processor |
| RPU1D processor | OCM_ASIL_D_CFG | Generated by the R5F processor |
| RPU0E processor | OCM_ASIL_D_CFG | Generated by the R5F processor |
| RPU1Eprocessor | OCM_ASIL_D_CFG | Generated by the R5F processor |
| ADMA | INTLPD_ASILD_CONFIG |
Individual channel registers: PS_DMA CH_DATA_ATTR |
| SDMA | INTLPD_ASILB_CONFIG |
Individual channel registers: PS_DMA CH_DATA_ATTR |
| AFI_FM | INTLPD_ASILB_CONFIG | |
| GEM0 | LPD_IOP_INT_CSR | LPD_IOP_SLCR (GEM0_IOU_COHERENT_CTRL) |
| GEM1 | LPD_IOP_INT_CSR | LPD_IOP_SLCR (GEM1_IOU_COHERENT_CTRL) |
| USB_XM0 | LPD_IOP_INT_CSR | |
| USB_XM1 | LPD_IOP_INT_CSR | |
| SYSMONROOT | PMC_INT_CFG | |
| DPC | PMC_INT_CFG | |
| JTAGDAP | PMC_INT_CFG | |
| PPU1 | PMC_INT_CFG | |
| PPU0 | PMC_INT_CFG | |
| PMCDMA0 | PMC_INT_CFG | |
| PMCDMA1 | PMC_INT_CFG | |