RX Descriptor Words - RX Descriptor Words - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)
Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

Received frames with optional FCS are written to receive buffers in system memory. The memory start location for each receive buffer is stored in the receive buffer descriptor table at an address location pointed to by the value in the receive-buffer queue pointer registers.

Each receive buffer start location is a word address. The start of the first memory buffer in a frame can be offset by up to three bytes depending on the value written to bits [14] and [15] of the network configuration register. If the start location of the AXI buffer is offset the available length of the first AXI buffer is reduced by the corresponding number of bytes.

There are six descriptor words per entry to provide a 44 or 48-bit address for the DMA AXI interface, see Descriptor Length.

Table 1. GEM RX Descriptor, Word 0
Bit Description
31:3 Starting RX memory buffer address, bits [31:3]. Bits [47:32] are held in descriptor entry word 3.
2

Timestamp enable:
0: None
1: Valid timestamp
1

Wrap enable:
0: No wrap
1: Wrap
0

Data ownership:
0: The controller can write data to the RX buffer
1: The controller sets this bit to 1 once the frame leaves the RXFIFO (written to system memory)
Software must clear this bit to 0 before the buffer can be used again.
Table 2. GEM RX Descriptor, Word 1
Field Description
31 Global all ones broadcast address detected.
30 Multicast hash match.
29 Unicast hash match.
28 I/O address match.
27 Specific type address register match found, bit [25] and [26] indicate the specific address register that caused the match.
26:25

Address register match indicator:
00: Specific address register 1 match
01: Specific address register 2 match
10: Specific address register 3 match
11: Specific address register 4 match

If more than one specific address is matched, only one is indicated with priority 4 down to 1.
24

Indicates different information when the RX checksum offloading is enabled or disabled.
• When RX checksum offloading is disabled, bit [24] is cleared and the network configuration type ID register match is found. Bit [22] and bit [23] indicates which type ID register caused the match.
• When RX checksum offloading is enabled, bit [24] is set in the network configuration.
0: Frame is not SNAP encoded and/or has a VLAN tag with the CFI bit set
1: Frame is SNAP encoded and has either no VLAN tag or a VLAN tag without the CFI bit set
23:22

Indicates different information when the RX checksum offloading is enabled or disabled.
• RX checksum offloading is disabled when the
            Network_Config
         [receive_checksum_offload_enable, 24] register bit = 0. The encoded matches are:
00: Type ID register 1 match
01: Type ID register 2 match
10: Type ID register 3 match
11: Type ID register 4 match

If more than one specific type ID is matched, only one is indicated with priority 4 down to 1.
• RX checksum offloading is enabled when Network_Config [24] bit is set = 1.
00: Both the IP header checksum and the TCP/UDP checksum were not checked
01: The IP header checksum is checked and is correct. Both the TCP or UDP checksum were not checked
10: Both the IP header and TCP checksum were checked and were correct
11: Both the IP header and UDP checksum were checked and were correct
21

VLAN tag detected: type ID of 0x8100. For packets incorporating the stacked VLAN processing feature, this bit is set if the second VLAN tag has a type ID of 0x8100.
20

Priority tag detected: type ID of 0x8100 and null VLAN identifier. For packets incorporating the stacked VLAN processing feature, this bit is set if the second VLAN tag has a type ID of 0x8100 and a null VLAN identifier.
19:17 VLAN priority: only valid if bit [21] is set.
16 Canonical format indicator (CFI) bit: only valid if bit [21] is set.
15

End of frame: when set, the buffer contains the end of a frame. If end of frame is not set, then the only valid status bit is start of frame bit [14].
14

Start of frame: when set, the buffer contains the start of a frame. If both bits [15] and [14] are set, the buffer contains a whole frame.
13

This bit has two different meanings depending on the Jumbo Frame Mode bit setting in the Network_Config register (see details in the table below).
12:0

Length of the received frame.

Note: The 4-byte FCS value at the end of the RX frame can be written to memory depending on the setting of the Network_Config [fcs_remove] bit 17.
Note: When jumbo frame mode is enabled, the frame size can be up to 10,240 bytes by using bit 13 of descriptor word 1 (above) for a total of 14 length bits.
Table 3. Descriptor Word 1, Bit 13 Details
Network_Config register Descriptor Word 1, Bit 13 Note
Bit 3, Jumbo Frame Mode Bit 26, Ignore FCS
0 0, don't ignore FCS
  • 0 (always): FCS indicates the frame written to memory is good
 When FCS is not ignored, only good frames are written to memory.
0 1, ignore FCS
  • 0: FCS indicates the written frame is good
  • 1: FCS indicates the written frame is bad
 Good and bad frames are written to memory.
1 x Length of jumbo frame: bit [13] concatenated with bits [12:0].  
Table 4. GEM RX Descriptor Word Summary
Word Field Description
Word 0 31:0 Timestamp enable, wrap enable, ownership.
Word 1 31:0 Miscellaneous fields.
Word 2 15:0 Upper sixteen AXI address bits [47:32].
31:16 Not used.
Word 3 31:0 Not used.
Word 4 29:0 Timestamp, nanoseconds.
31:30 Timestamp, seconds, bits [1:0].
Word 5 3:0 Timestamp, seconds, bits [5:2].
31:4 Not used.