RPU Functional Units - RPU Functional Units - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The following table lists the RPU subsystem functional units.

Table 1. RPU Subsystem Functional Units
Unit Description Note and Link
Compute Resources and Memory
Real-time processing unit Up to ten-core-processor Arm Cortex-R52 with lock-step option 1  
Tightly-coupled memories Three tightly-coupled memories (TCMs) per RPU CPU core provides a deterministic, low-latency memory space (128 KB total per core)
OCM RAM Up to four-bank, 2 MB memory 1
LPD DMA 0 General purpose DMA unit 0 with simple and linked-list functionality
LPD DMA 1 General purpose DMA unit 1 with simple and linked-list functionality
System watchdog timers (SWDTs) SWDTs for software integrity monitoring, one for each RPU cluster
Support Units
Interconnect (INT) OCM switch, main switch, peripheral switch
Memory protection units (XMPUs) Configurable transaction firewall with 4 KB or 1 MB apertures
Peripheral protection units (XPPUs) Configurable transaction firewall with 64 KB, 1 MB, and 512 KB apertures
System counters Global timer reference for software
I/O Peripheral Controllers
LPD GPIO General purpose I/O controller (26 MIO channels, 32 EMIO channels)
USB Dual universal serial bus controller v2.0
Gigabit Ethernet MAC (GEM) Dual GEM controllers
  1. For device-specific features, such as RPU cluster configuration and on-chip memory details, see the Versal Architecture and Product Data Sheet: Overview (DS950).