Initialization
The gigabit enable bit [10] in the network configuration register selects between 10/100 Mb/s Ethernet operation using MII or SGMII interface and 1 Gigabit operation using GMII or SGMII interface.
The MAC transmit and receive data paths are configured by the network configuration register bits [10, gigabit_mode_enable] and [11, pcs_select] for different modes and speeds of operation.
The controller speed of operation is configured through hs_mac register [2:0] bits and Serdes rate through usx_control_register [13:12] and USXGMII speed through [16:14]. These bits along with the serdes_rate field will determine the amount of replication performed to obtain the desired sub-rate.
If the high speed MAC is set through network control register bit [31], the maximum line rate of the controller is set using the High-Speed MAC configuration register at 0x0050.
Receive and Transmit Buffer
Receive Buffer
- Allocate a number (N) of buffers of X bytes in system memory, where X is the DMA buffer length programmed in the DMA Configuration register.
- Allocate an area 8NxM bytes for the receive buffer descriptor list in system memory and create N entries in this list. Mark all entries in this list, except for the last one, as owned by GEM, that is bit 0 of word 0 set to 0.
- For the last descriptor set the used and wrap bits, (bits 0 and 1 in word 0 set to 1). When receive is enabled at least one entry in the buffer descriptor ring needs its used bit set so it is not sufficient to set the wrap bit of the last buffer in the queue without also setting its used bit. 10GbE can prefetch receive descriptors and the used bit will be used as an indication to the hardware that all available descriptors have been prefetched. As frames are received and processed firmware clears the used bits ensuring at least one used bit is always set.
- Write address of receive buffer descriptor list and control information to GEM register receive buffer queue pointer.
- The receive circuits can then be enabled by writing to the address recognition registers and the network control register.
Transmit Buffer
- Allocate a number (N) of buffers of between 0 and 16380 bytes of data to be transmitted in system memory. Up to 128 buffers per frame are allowed.
- Allocate an area 8NxM bytes for the transmit buffer descriptor list in system memory and create N entries in this list. Mark all entries in this list as owned by GEM, i.e. bit 31 of word 1 set to 0.
- Add an extra descriptor to the end of queue with its used bit set (bit 31 in word 1 set to 1). This last descriptor in the queue may also have its wrap bit set (bit 1 in word 0 set to 1) in addition to its used bit. When transmit is enabled at least one entry in the buffer descriptor ring must have its used bit set. When the buffer descriptor ring is initialized for the first time there must be a used bit set before or at the buffer descriptor with the wrap bit. Once transmission halts due to reading a used bit firmware can reuse the transmit buffers and clear the used bits before and including the one with the wrap bit and restart transmission by writing the tx_start bit.
- 10GbE can now read transmit data so fast that all data may be read in before it sets the used bit of the first buffer descriptor in the queue.
- Write address of transmit buffer descriptor list and control information to 10GbE register transmit buffer queue pointer.
- The transmit circuits can then be enabled by writing to the network control register.
Transmitting Frames
To set up a frame for transmission:
- Allocate an area of system memory for transmit data. This does not have to be contiguous, varying byte lengths can be used if they conclude on byte borders.
- Write the address of the first buffer descriptor to transmit buffer descriptor queue pointer. When priority queues are used, each queue’s buffer descriptor queue pointer should be updated and Q0’s pointer should be updated last of all.
- Enable transmit bit [3] in the network control register.
- Set-up the transmit buffer list by writing buffer addresses to word zero of the transmit buffer descriptor entries and control and length to word one. Make sure there is an extra dummy descriptor at the end of the list with its “used bit” set.
- Write data for transmission into the buffers pointed to by the descriptors.
- Enable appropriate interrupts
- Write to the transmit start bit [9] in the network control register, or toggle the trigger_dma_tx_start pin
Receiving Frames
When receive frames are enabled through bit [2] in the network control register and a frame is received , 10GbE checks the address and, in the following cases, the frame is written to system memory if:
The register receives buffer queue pointer points to the next entry in the receive buffer descriptor list and 10GbE uses this as the address in system memory to write the frame to. Once the frame has been completely and successfully received and written to system memory, GEM then updates the receive buffer descriptor entry with the reason for the address match and marks the area as being owned by software. Once this is complete, a receive complete interrupt is set. Software is then responsible for copying the data to the application area and releasing the buffer (by writing the ownership bit back to 0).
If 10GbE is unable to write the data at a rate to match the incoming frame, then a receive overrun interrupt is set. If there is no receive buffer available, that is, the next buffer is still owned by software, a receive buffer not available interrupt is set. If the frame is not successfully received, the receive overrun statistic register is incremented and the frame is discarded without informing software.