This section summarizes the programming of the PCI Express controller for Endpoint and Root port operations.
Programming the PS-GTYP
The following steps are used to program the PS-GTYP interface to support the PCI Express protocol:
- Assign PS-GTYP lanes to the PCIe PHY that presents a PIPE interface to the controller for PCIe
- Program SERDES.ICM_CFG0 and SERDES.ICM_CFG1 to support the PCIe protocol lanes as per the requirement
- Set the PLL reference clock to 100 MHz: SERDES.PLL_REF_SEL0 = 0x0D
Programming the Reset Pin
Program the MIO registers in the IOU_SLCR module to configure the PCIe reset pin. For Endpoint mode, the PCIe reset pin is configured as an input. For Root Port mode, the PCIe reset pin is configured as an output.
- For Endpoint mode, use one of PMC_MIO_[7,8,30,38] or LPD_MIO_[3,8] from the IOU_SLCR module as the PCIe reset input (based on board layout). The input reset signals are listed in the MIO pin assignment tables in chapter 26.
- For Root Port mode, use any GPIO to map the reset output, which is driven by software.
Programming the Controller
The following steps describe the sequence of operations to program the PCI Express controller:
- Select MMI_PIPE_GEM_SLCR.MODE to Required Configuration
- Program the MMI_CRX.RST_PCIE(0xedc00304) or MMI_CRX.RST_PCIE1(0xedc00308) register to release pcie_reset
- Program the integrated block for PCIe to the Endpoint or Root Port role using the APB interface. The default values in the registers are for Endpoint mode.
- For Root Port mode, set the BAR and the memory base/limit registers to defaults for Root Port.
- For Endpoint mode, the BAR settings are dependent on user selection
such as size, prefetchable or not, etc.
- Change the class code
- Change the device port type to Root Port
- For the case of MMI_PCIe0_SLCR.General_cfg.Typr = 0x1:
- Change the Next pointer for PM capability to point to PCIe capability
- Disable the MSI capability
At this point, the controller is ready to initiate link training with a link partner, once pcie_reset_n (PERST#) is released by the board or the host.
Endpoint Mode DMA Operation
This section describes the DMA operation when the PCIe controller is used as an Endpoint. The DMA Operation section describes the dataflow for this mode. Once the core is configured for Endpoint mode of operation, the DMA activity can be divided into three phases.
- Initialization Phase: Initializes the DMA channel, sets up the descriptor elements
- DMA Phase: The DMA operation is executed.
- Exit Phase: the DMA transaction completes and the allocated resources are released.
Terminology:
PFX_HDMA_CAP_HDMA_STATUS_OFF_WRCH_i
PFX_HDMA_CAP_HDMA_STATUS_OFF_RDCH_i
The 'X' refers to the physical function
The 'i' refers to the channel index within the mentioned physical function
Sequence to Enable DMA Channel
The following DMA channel enable sequence is recommended:
- Ensure that the DMA is in an idle state by reading the STATE field of PFX_HDMA_CAP_HDMA_STATUS_OFF_[WRCH | READ]_i and confirming that it has value b11
- Enable the channel by setting the EN (bit 0) to PFX_HDMA_CAP_HDMA_EN_OFF_[WRCH | READ]_i
DMA Operation
The DMA channel executes the DMA transactions by reading the descriptors from the linked list associated with the corresponding channel in the Endpoint's memory. The address of the start of the linked list's last element needs to be configured in the Load Link Pointer (LLP) register. For the simple mode, the SAR, DAR and XFER_SIZE registers can be configured. Refer to the following flow diagram of the DMA operation:
Scatter Gather Mode of Programming
DMA supports Link List mode for scatter-gather mode.
Linked List Mode Use Case
To facilitate DMA data transfers using the linked list mode, the following steps are necessary. The linked-list mode can be used when software cannot find a contiguous set of memory that can accommodate all the buffer descriptors necessary (source and destination) as an array. The linked list is the BAR region mapped onto the memory associated with the Endpoint.
Step 1:
Enable the DMA channel by setting the EN (bit 0) of PFX_HDMA_CAP_HDMA_EN_OFF_[WRCH | READ]_i
Step 2:
The descriptor information is written to the linked list. The size of the linked list is pre-configured. This linked list need to be populated before issuing the commands in the next steps.
Step 3:
Enable an interrupt by setting the MASK (bit 0), RSIE (bit 3) OR LSIE (bit 4) to 1 in the PFX_HDMA_CAP_HDMA_INT_SETUP_OFF_[WRCH | RDCH]_i register.
Step 4:
a. Ensure that LLEN (bit 0) of the PFX_HDMA_CAP_HDMA_CONTROL1_OFF_[WRCH | RDCH]_i register is 1.
b. The address of the first buffer descriptor in a list is written to PFX_HDMA_CAP_HDMA_LLP_LOW_OFF_[WRCH | RDCH]_i and PFX_HDMA_CAP_HDMA_LLP_HIGH_OFF_[WRCH | RDCH]_i.
c. Set the CYCLE_STATE (bit 1) and CYCLE_BIT (bit 0) in PFX_HDMA_CAP_HDMA_CYCLE_OFF_[WRCH | RDCH]_i. The CYCLE_BIT is set for recycling the linked list. CYCLE_STATE is used for synchronizing the producer-consumer cycle.
Step 5:
Enable the DMA channel to perform DMA transfers by setting the EN (bit 0) of PFX_HDMA_CAP_HDMA_DOORBELL_OFF_[WRCH | RDCH]_i.
IMPORTANT: The minimum linked list size is 2 elements for the linked list mode.
A linked list size of N has N elements : [0], [1], ..., [N-1]. For example, a linked list of size 2 has [0] and [1] elements. The last element of the linked list is used for Load Link Pointer (LLP) so the effective size of linked lists for storing descriptors is N-1.
The linked list wraps at N-2 element. For example, for a linked list size of 4, the wrap occurs as: [0], [1], [2], [0], [1], ...
RECOMMENDED: The DMA linked lists are intended to be initially setup and reused for multiple DMA operations. The DMA linked lists are designed to enable highly overlapped transactions. Software can setup new DMA operations in the linked list while the DMA channel is executing operations that the software placed in the linked list earlier.
Simple Mode Programming
Step 1
Enable the channel by setting the EN (bit 0) of PFX_HDMA_CAP_HDMA_EN_OFF_[WRCH | READ]_i
Step 2
Ensure that LLEN (bit 0) of the PFX_HDMA_CAP_HDMA_CONTROL1_OFF_[WRCH | RDCH]_i register is 0.
Program the data source buffer address LSB into register PFX_HDMA_CAP_HDMA_SAR_LOW_OFF_[WRCH | RDCH]_i .
Program the data source buffer address MSB into register PFX_HDMA_CAP_HDMA_SAR_HIGH_OFF_[WRCH | RDCH]_i .
Step 3
Program the data destination buffer address LSB into register PFX_HDMA_CAP_HDMA_DAR_LOW_OFF_[WRCH | RDCH]_i .
Program the data destination buffer address MSB into register PFX_HDMA_CAP_HDMA_DAR_HIGH_OFF_[WRCH | RDCH]_i .
Step 4
Program the data size into the PFX_HDMA_CAP_HDMA_XFERSIZE_OFF_[WRCH | RDCH]_i register.
Step 5
Enable an interrupt by setting MASK (bit 0), RSIE (bit 3) OR LSIE (bit 4) to 1 in the PFX_HDMA_CAP_HDMA_INT_SETUP_OFF_[WRCH | RDCH]_i register.
Step 6
Enable the DMA channel to perform DMA transfers by setting the EN (bit 0) of PFX_HDMA_CAP_HDMA_DOORBELL_OFF_[WRCH | RDCH]_i.
NOTE: The channel context registers such as LLP, SAR, DAR, XFER_SIZE must not be written after the DB_START has been set. Doing so would result in unexpected behavior.
Descriptor Post-processing
When a DMA transaction completes (software reads the current DMA completion status by reading the channel status register) in scatter-gather mode, software processes the resulting DMA data and recycles the linked list elements associated with the transfer request. The recycling happens upon reading the CYCLE_BIT state in the LLP registers.
Disabling an Active DMA Channel
The preferred process to disable an operational DMA channel is as follows:
- Software stops adding new DMA transfers to the linked list if scatter-gather mode is used
- Wait for the outstanding DMA request
- MASK the bits in PFX_HDMA_CAP_INT_SETUP_OFF_[WRCH | RDCH]_i registers
- Clear the bits in PFX_HDMA_CAP_INT_CLEAR_OFF_[WRCH | RDCH]_i registers
- Disable the channel by setting bit(0) to 0 in PFX_HDMA_CAP_HDMA_EN_OFF_[WRCH | READ]_i