Programming Considerations - Programming Considerations - AM026

Programming Sequence

The Display Controller can be setup with the following steps for non-live mode, other sequences are also possible. For instructions to program the display controller and running the software application, refer to the Processing System Wizard v1.0 LogiCORE IP Product Guide (PG450).

• Reset the complete system for initialization.
• Program the DP sequence according to the resolution and video formats.
• For normal DC operation
  • Program DC with the required video resolution: 0xEDD0_0000 – 0xEDD0_0020
  • Program Video Pipeline (Blender)
    • To configure input color space conversion matrix coefficients
      • Stream 1: 0xEDD0_A044 – 0xEDD0_A064, stream 2: 0xEDD0_A080 – 0xEDD0_A0A0
    • To configure input color space conversion matrix offsets
      • Stream 1 : 0xEDD0_A068 – 0xEDD0_A070, stream 2 : 0xEDD0_A0A4 – 0xEDD0_A0AC
    • To configure output color space conversion matrix coefficients: 0xEDD0_A020–0xEDD0_A040
    • To configure output color space conversion matrix offsets: 0xEDD0_A074 – 0xEDD0_A07C
    • To configure video blender function, stream 1: 0xEDD0_A018, stream 2: 0xEDD0_A01C
    • To select output format: 0xEDD0_A014
• Program clock source selection: 0xEDD0_CC5C, 0xEDD0_B120
• Issue a soft reset after clock source selection changes: 0xEDD0_B124
• Program live video format – color space and color depth: 0xEDD0_B224, 0xEDD0_B234
• Program live pixel scaling: 0xEDD0_B218 – 0xEDD0_B220, 0xEDD0_B228 – 0xEDD0_B230
• Program non-live video format – color space and color depth: 0xEDD0_B000
• Program non-live pixel scaling: 0xEDD0_B200 – 0xEDD0_B208, 0xEDD0_B20C – 0xEDD0_B214
• Program audio/video live/non-live selection: 0xEDD0_B070
• Program AV Buffer Manager as per stream requirements: 0xEDD0_B010 – 0xEDD0_B024
  • Flush the buffer
  • Enable and program Burst length (see Programming options below for guidance)
• Wait for one vsync or one video frame time, this is a required step for cursor
• Program cursor and SDP: 0xEDD0_CC1C – 0xEDD0_CC28
• Program partial plane blending as needed: 0xEDD0_CC2C – 0xEDD0_CC44
• Program audio:
  • Live or non-live audio selection: 0xEDD0_B070
  • Audio clock and control: 0xEDD0_CC60 – 0xEDD0_CC68
  • Audio soft reset: 0xEDD0_CC00
  • Audio channel buffer control: 0xEDD0_CC08
• Audio channel selection
  • 0xEDD0_CC0C [2:0] =3’d7 (the only supported value)
  • 0xEDD0_CC0C [14:3] =12’h1ff (the only supported value)
  • 0xEDD0_C000[7:0] – 1 bit per channel, channel 0 at LSB, active 0, inactive 1
• Audio channel status and user bit data (see also Section 1.14.4)
  • 0xEDD0_C000[8] – 0 before programming data, 1 – after programming data
  • 0xEDD0_C008 – 0xEDD0_C124
• Program the DMA for non-live video and audio as required: 0xEDD1_0204 – 0xEDD1_0918
  • Enable and trigger the DMA controllers to start non-live video: 0xEDD1_0104
  • The relevant video DMA controllers should be triggered at the same time to make sure they start operating concurrently.

Programming Notes

1. Changing Burst length (BL) on the fly is not supported. It is expected that, once a burst length is chosen by the user, it is kept unchanged. If the user has to change BL, then the above programming sequence has to be followed. The same applies to changes in video resolution and pixel format change.
2. The suggested programming sequence is :
   1. Program AV Buffer Manager
   2. Program DMA
3. Similarly, when disabling
   1. Disable DMA (see (5) to cleanly disable an operating DMA channel)
   2. Disable channel and output stream in AV Buffer Manager
4. When blending is enabled, make sure to program “RGB_MODE” bit of Layer0 and Layer 1 control registers (0xEDD0_A018 and 0xEDD0_A01C). If blender output is RGB data, this bit must be set to 1. For YUV this bit should be ‘0’.
5. Follow the steps below to cleanly disable a DMA channel and to avoid hung transactions.
   1. In the DMA descriptor
      1. set the last_descriptor bit. This will return the DMA FSM to the idle condition once the descriptor is done.
      2. set the Enable Interrupt bit. This will assert the dscr_done interrupt status in 0xEDD1_0050 when there are no more outstanding transactions after processing the last descriptor.
   2. Once the interrupt has triggered, the DMA channel EN bit in 0xEDD1_0218 should be set to 0 to disable further DMA transfers.