The peripheral protection unit (XPPU) in the Versal adaptive SoC is similar to the one in the Zynq UltraScale+ MPSoC except in the way an error is handled. The default setting is to deny a transaction.
| Device Generation | Isolation, Parity, Protection, and Integrity Checking | Error Handling | Total Number of Apertures | Dynamic Reconfiguration |
|---|---|---|---|---|
| UltraScale+ MPSoC | Inserted on AXI channels | Poison the base address |
128x 32 B (IPI msg buffer) |
No |
| Versal device | Embedded into interconnect switches | Issue a fail message on the interconnect back to initiator |
~ |
Yes |
| Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 | Embedded into interconnect switches | Yes |