PS High-Speed Connectivity Signals and Interfaces - PS High-Speed Connectivity Signals and Interfaces

PS High-Speed Connectivity Signals and Interfaces - PS High-Speed Connectivity Signals and Interfaces - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID

AM026

Release Date

2025-12-23

Revision

1.3 English

The tables below describe device pins and major signals and interfaces that cross between Programmable Logic (PL) and Processing System (PS) power domains.

Dedicated Device Pins

Table 1. Power Pins
Pin Name	Description
VCC_USB2	USB2_PHY 0.8V Fixed Voltage
VCC_PAUX	AUXP_PHY 0.8V Fixed Voltage
VCC_USB3	USB3_PHY 0.8V Fixed Voltage
VCCIO_USB2	USB2_PHY 3.3V Fixed Voltage
VCCREG_USB2	USB2_PHYREG 3.3 Fixed Voltage
VCCIO_PAUX	AUXP_PHY 1.8V Fixed Voltage
VCCIO_USB3	USB3_PHY 1.2 or 1.8V Fixed Voltage
The required sequencing, power delivery options, and decoupling requirements based on design are found in the Power Design Manager (PDM) tool (download at www.amd.com/power).

Table 2. USB IO Pins
Pin Name	Direction	Type	Description
PAD_AUX_PADN	Inout	Dedicated	AUX pin used for perform AUX transactions
PAD_AUX_PADP	Inout	Dedicated	AUX pin used for perform AUX transactions
PAD_USB2_DM0	Inout	Dedicated	D minus pin : Data transfer pin of USB2
PAD_USB2_DP0	Inout	Dedicated	D plus pin : Data transfer pin of USB2
PAD_USB2_ID0	Inout	Dedicated
PAD_USB2_VBUS0	Inout	Dedicated	Voltage bus pin
PAD_USB3_PHY_REF_PAD_CLK_M	In	Dedicated	Low-Swing differential Input Clock pair with PAD
PAD_USB3_PHY_REF_PAD_CLK_P	In	Dedicated	Low-Swing differential Input Clock pair with PAD
PAD_USB3_PHY_RESREF	Inout	Dedicated	Reference Resistor Connection
PAD_USB3_PHY_TX0_M	Out	Dedicated	High Speed Differential Transmit Pair for Lane 0
PAD_USB3_PHY_TX0_P	Out	Dedicated	High Speed Differential Transmit Pair for Lane 0
PAD_USB3_PHY_TX3_M	Out	Dedicated	High Speed Differential Transmit Pair for Lane 3
PAD_USB3_PHY_TX3_P	Out	Dedicated	High Speed Differential Transmit Pair for Lane 3
PAD_USB3_PHY_TXRX1_M	Inout	Dedicated	High Speed Differential Receive pair for Lane 1 TX for DP Mode and RX for USB Mode
PAD_USB3_PHY_TXRX1_P	Inout	Dedicated	High Speed Differential Receive pair for Lane 1 TX for DP Mode and RX for USB Mode
PAD_USB3_PHY_TXRX2_M	Inout	Dedicated	High Speed Differential Receive pair for Lane 2 TX for DP Mode and RX for USB Mode
PAD_USB3_PHY_TXRX2_P	Inout	Dedicated	High Speed Differential Receive pair for Lane 2 TX for DP Mode and RX for USB Mode
If USB is unused, tie the PAD_USB3_PHY_REF_PAD_CLK_P and PAD_USB3_PHY_REF_PAD_CLK_M pins low, and keep remaining USB pins floating.

PS High-Speed Connectivity to PL Interfaces

Table 3. 10GbE Signals and Interfaces
Name	Count	Source	Destination	Description
10GBE FIFO	35 Signals	10GbE, PL	10GbE, PL	Ethernet RX and TX packet Streams
10GBE 1588 PTP	10 Signals	10GbE	PL	PTP event frame interface
10GBE TSU	2 Signals	10GbE	PL	Ethernet 94-bit IEEE 1588 timestamp read by PL interface

Table 4. DisplayPort Signals and Interfaces
Name	Count	Source	Destination	Description
Video	50 Signals	PS High-Speed Connectivity, PL	PL, PS High-Speed Connectivity	Eight 36-bit input Native Video Streams to PS High-Speed Connectivity from PL. Two 36-bit Output Native Video Streams to PL from PS High-Speed Connectivity
Audio	10 Signals	PS High-Speed Connectivity, PL	PL, High-Speed Connectivity	Four Input I2S Serial Audio Interfaces to PS High-Speed Connectivity from PL. One Output I2S Serial Audio Interface to PL from PS High-Speed Connectivity
SDP (Secondary Data Packet)	46 Signals	PS High-Speed Connectivity, PL	PL, PS High-Speed Connectivity	Five Input SDP Interfaces to PS High-Speed Connectivity from PL Two Output SDP Interfaces to PL from PS High-Speed Connectivity

Table 5. Clock Signals
Name	Count	Source	Destination	Description
10GBE_PL_CLK	6	PS High-Speed Connectivity, PL	PL, PS High-Speed Connectivity	Two input TX and RX Clock Two Output TX and RX Clock Two TSU Clocks
VIDEO CLK	5	PL	PS High-Speed Connectivity	1x (300 MHz) and 2x(600 MHz) Video Clock to Display Controller And another Three 300 MHz Clocks to Display Port
AUDIO CLK	4	PL	PS High-Speed Connectivity	Four Audio Clocks with Frequency 192 kHz x 512
DEBUG CLK	2	PS High-Speed Connectivity, PL	PL, PS High-Speed Connectivity	300 MHz Debug Clock

Table 6. Interrupt Signals
Name	Count	Source	Destination	Description
PL IRQs	5	PS High-Speed Connectivity, PL	PL, PS High-Speed Connectivity	Three IRQ from PS High-Speed Connectivity to PL Two General Purpose IRQ input signals

Table 7. Debug Signals
Name	Count	Source	Destination	Description
PL Debug	1	PS High-Speed Connectivity	PL	260-bit Debug Data output to PL

Table 8. Miscellaneous Signals
Name	Count	Source	Destination	Description
PL SPARE	2	PS High-Speed Connectivity, PL	PL, PS High-Speed Connectivity	One 32-bit Input Spare signal One 32-bit Output Spare Signal
GPIO	2	PS High-Speed Connectivity, PL	PL, PS High-Speed Connectivity	One 16-bit Input GPI Signal One 32-bit Output GPO Signal