PS High-Speed Connectivity Clocking and Reset Subsystem - PS High-Speed Connectivity Clocking and Reset Subsystem - AM026

Introduction

The High-Speed Connectivity clocking and reset system generates clocks and Resets for the peripherals, interconnect, and other system elements. There are two system PLLs to generate high-frequency signals that are used as clock sources for the several clock generators in MMI.

System PLL Units

There are two PLL in the High-Speed Connectivity Module. Each PLL has suggested usage:

• MMI PLL: There are two modes for this PLL which generates clocks for different Subsystems
  • Normal Mode: Provides Core clock to GPU Subsystem and MMI Debug Clock. Display Controller will use clocks from PL
  • DC Internal Mode: Provides Video clock and Timestamp clock to Display Controller and MMI Debug Clock. GPU will use the PS_AXI_DMA_CLK.

• UDH PLL: Provides clock to USB and DisplayPort Subsystems.

Refer to the following figure for the PS High-Speed Connectivity clock diagram that shows the two PLL and internal muxes that generate various clocks to the peripherals.

The following table shows the PS High-Speed Connectivity peripheral clock frequency (at 2MP speedgrade) generated by the 2 PLLs.

System Resets

The High-Speed Connectivity module has two pin level reset and several register level block resets. The reset sequences are divied into three functional areas.

• The power-on reset sequence.
• The management of other signals in the system to trigger system reset.
• The ability (in software) to reset each individual functional unit.

Clock Programming

System PLL Operation

The voltage-controlled oscillator (VCO) in the PLL synthesizes the output frequency based on the feedback multiplier. The VCO supports both fractional and integer multipliers. The fractional mode is enabled by setting PLL_FRAC_CFG[ENABLED] to 1.

The VCO output frequency (F_VCO) is determined using the following equation.

F_VCO = F_REFCLK x M.F

In this equation, the F_REFCLK is an input reference clock frequency, M is the integer part of the multiplier value, and F is the fractional part.

The output frequency (F_CLKOUT), after the divider stage, is determined by the following equation.

F_CLKOUT = F_VCO/O

In this equation, O is the 10-bit output divider

PLL Programming Sequence

1. Program FBDIV and CLKOUTDIV in MMIPLL_CTRL Register
2. Program Helper Data for MMIPLL_CFG using the helper data in Helper Data Table
3. Assert Bypass
4. Assert Reset. This is when the values of FBDIV and CLKOUTDIV captured into PLL
5. De-assert Reset
6. Check for LOCK. Wail until PLL_STATUS[LOCK] = 1
7. De-assert Bypass
8. Program divider by programming DIVISOR0 field of Clock Generator Control registers.

PLL Integer Divide Helper Data Table

For each unique value multiplier value, program the PLLs using registers in the MMI_CRX and MMI_UDH_PLL register sets. Each of the two PLLs have a set of integer programming parameters:

• {MMI, UDH}_PLL_CFG[CP]
• {MMI, UDH}_PLL_CFG[RES]
• {MMI, UDH}_PLL_CFG[LFHF]
• {MMI, UDH}_PLL_CFG[LOCK_DLY]
• {MMI, UDH}_PLL_CFG[LOCK_CNT]

The helper data values provides the PLL configuration register programming values when the PLL is in integer mode.

Clock Configuration Register Overview

System PLL Control Registers

Reset Configuration Register Overview

The following table describes the registers that can be used to configure resets for different peripherals.