PPU Implementations - PPU Implementations - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The following table shows the PPU implementations.

Table 1. PPU Implementations
Device Generation Platform Processor Unit Processor RAM
UltraScale+ MPSoC MicroBlaze platform management unit (PMU), single CPU core 128 KB PMU RAM
Versal device MicroBlaze platform processor unit (PPU), TMR core 384 KB PPU RAM
Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 MicroBlaze platform processor unit (PPU), TMR core 512KB (plus ECC) of instruction RAM and 128KB (plus ECC) of data RAM