PMC MIO Pin Tables - PMC MIO Pin Tables - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The following tables list the PMC MIO pin assignments.

Table 1. PMC MIO Pin Assignments (Bank 500)
Pins: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PMC Controllers:
OSPI Boot CLK IO 0 IO 1 IO 2 IO 3 IO 4 DS IO 5 IO 6 IO 7 CS0 CS1 RST ECC
QSPI Boot CLK0 IO0 1 IO0 2 IO0 3 IO0 0 CS0 LPBK CS1 IO1 0 IO1 1 IO1 2 IO1 3 CLK1
SD v3.0 Boot D 0 D 1 D 2 D 3 PWR CLK SEL DIRC DIR 0 DIR 1 CMD CD WP
eMMC CMD D 0 D 1 D 2 CLK D 3 D 4 D 5 D 6 D 7 DS RST
UFS CD CFG CLK RST CFG CLK RST
SMAP IO 0 IO 1 IO 2 IO 3 CLK CS RW BSY IO 4 IO 5 IO 6 IO 7
SysMon I2C/SMB SCL SDA SMB SCL SDA SMB SCL SDA SMB SCL SDA SMB SCL SDA SMB SCL SDA SMB
Tamper Trig TRIG TRIG TRIG TRIG
PMC GPIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
LPD Controllers:
CANFD RX 0 TX 0 TX 1 RX 1 RX 2 TX 2 RX 3 TX 3 RX 0 TX 0 TX 1 RX 1 RX 2 TX 2 RX 3 TX 3 RX 0 TX 0 TX 1 RX 1 RX 2 TX 2 RX 3 TX 3
LPD I3C 0 SCL SDA SCL SDA
LPD I3C 1 SCL SDA SCL SDA
PCIE n RST0 RST1
SPI 0 SCLK CS2 CS1 CS0 MISO MOSI SCLK CS2 CS1 CS0 MISO MOSI
SPI 1 SCLK CS2 CS1 CS0 MISO MOSI SCLK CS2 CS1 CS0 MISO MOSI
TRACE CTL D 0 CLK D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15
SWDT INT INT INT
TTC n

CLK 1

WA  1

CLK 0

WA 0

CLK 3

WA 3

CLK 1

WA 1

CLK 0

WA 0

CLK 2

WA 2

CLK 1

WA 1

CLK 0 WA 0
UART 0 RXD TXD CTS RTS RXD TXD CTS RTS RXD TXD CTS RTS
UART 1 TXD RXD CTS RTS TXD RXD CTS RTS TXD RXD CTS RTS
USB 0 ULPI RST D 0 D 1 D 2 D 3 CLK D 4 D 5 D 6 D 7 DIR STP NXT
Table 2. PMC MIO Pin Assignments (Bank 501)
Pins: 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
PMC Controllers:
OSPI Flash ECC
SD v2.0 Boot PWR CMD D 0 D 1 D 2 D 3 CLK CD WP
SD v3.0 Boot PWR CMD D 0 D 1 D 2 D 3 CLK SEL DIRC DIR 0 DIR 1 CD WP                  
eMMC Boot CMD D 0 D 1 D 2 CLK D 3 D 4 D 5 D 6 D 7 DS RST
UFS CD CFG CLK RST CD CD RST CFG CLK
SMAP IO 8 IO 9 IO 10 IO 11 IO 12 IO 13 IO 14 IO 15 IO 16 IO 17 IO 18 IO 19 IO 20 IO 21 IO 22 IO 23 IO 24 IO 25 IO 26 IO 27 IO 28 IO 29 IO 30 IO 31
SMP
SysMon I2C/SMB SCL SDA SMB SCL SDA SMB SCL SDA SMB SCL SDA SMB
Tamper Trig TRIG TRIG
PMC GPIO 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
LPD Controllers:
CANFD RX 0 TX 0 TX 1 RX 1 RX 2 TX 2 RX 3 TX 3 RX 0 TX 0 TX 1 RX 1 RX 2 TX 2 RX 3 TX 3 RX 0 TX 0 TX 1 RX 1 RX 2 TX 2 RX 3 TX 3
GEM 0 RGMII TX CLK TXD 0 TXD 1 TXD 2 TXD 3 TX CTL RX CLK RXD 0 RXD 1 RXD 2 RXD 3 RX CTL
GEM 0 RMII TXD 0 TXD 1 TX EN REFCLK RXD 0 RXD 1 RX ERR CRS DV
GEM 1 RGMII TX CLK TXD 0 TXD 1 TXD 2 TXD 3 TX CTL RX CLK RXD 0 RXD 1 RXD 2 RXD 3 RX CTL
GEM 1 RMII TXD 0 TXD 1 TX EN REFCLK RXD 0 RXD 1 RX ERR CRS DV
GEMn MDIO - - - - 0,1 CLK 0,1 DATA
GEM TSU CLK CLK
LPD I3C 0 SCL SDA SCL SDA
LPD I3C 1 SCL SDA SCL SDA
PCIEn RST0 RST1
SPI 0 SCLK CS2 CS1 CS0 MISO MOSI SCLK CS2 CS1 CS0 MISO MOSI
SPI 1 SCLK CS2 CS1 CS0 MISO MOSI SCLK CS2 CS1 CS0 MISO MOSI
TRACE CTL D 0 CLK D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15
SWDT INT INT
TTC n

CLK 1

WA 1

CLK 0

WA 0

CLK 3

WA 3

CLK 2

WA 2

CLK 1

WA 1 CLK 1 WA 1 CLK 0 WA 0
UART 0 RXD TXD CTS RTS RXD TXD CTS RTS RXD TXD CTS RTS
UART 1 TXD RXD CTS RTS TXD RXD CTS RTS TXD RXD CTS RTS
USB 1 ULPI RST D 0 D 1 D 2 D 3 CLK D 4 D 5 D 6 D 7 DIR STP NXT
MMI MMI HPD