PMC I/O Signals - PMC I/O Signals - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The PMC I/O connections facilitate boot, system management, and other functions. Each device has dozens of pins associated with the PMC. There are dedicated I/O pins. The remaining pins are configurable PMC multiplexed I/O (MIO) pins that support the flash memory and I/O peripheral interfaces.

The I/O peripherals and SD/eMMC flash memory controllers can interface to the PL's HDIO pins by using the EMIO routing. When the route through the PL is used, the LPD and PL power domains must be powered up. For more information on the PMC I/O pins, see Signals, Interfaces, Pins, and Controls.

PMC I/O Signal Diagram Notes

Note: There are two PMC_I3C controllers. Their interfaces are on the PMC dedicated I/O pins (not shown in the figure).
Figure 1. PMC I/O Signals