The following table lists the PMC functional units.
| Unit | Description | Link |
|---|---|---|
| Compute Resources | ||
| ROM code unit | Executes BootROM code after a POR or system reset | RCU ROM Code Unit |
| Platform processing unit | Executes platform loader and manager firmware | PPU MicroBlaze Processor |
| PPU RAM | Partitioned 512 KB instruction and 128 KB data memory (640 KB total) | – |
| PMC RAM | 128 KB system memory for use by PLM | – |
| PMC DMA 0 and 1 | Streams data between secure switch and main switch | PMC DMA Units and Stream Switch |
| Support Units | ||
| IPI | Inter-processor interrupts | Inter-Processor Interrupts |
| System interrupts | System interrupts to PPU interrupt controller for PLM firmware | System Interrupts |
| Service request registers | Runtime service requests | – |
| PMC EAM | PMC error accumulator module | System Errors |
| Interconnect | ||
| Interconnect (INT) | Switches: main, I/O peripheral, auxiliary, and APB | – |
| PMC_RAM_XMPU PMC_SBI_XMPU PMC_CFU_XMPU |
Memory protection unit for PMC RAM, SBI, and CFU | – |
| PMC_XPPU PMC_NPI_XPPU |
Peripheral protection unit for PMC and NPI-based register modules | – |
| APB | Register programming interfaces: 32-bit single read/write | APB and AXI Programming Interfaces |
| NPI | Register programming interfaces: 32-bit with read/write burst | NPI Programming Interface |
| Configuration | ||
| PL CFU | PL configuration frame unit | Configuration Frame Unit |
| eFUSE controller |
Controller for eFUSE array |
– |
| eFUSE cache |
Cache of the eFUSEs |
– |
| PMC_SBI | Boot interface works with SelectMAP and JTAG data flows | SBI for JTAG and SelectMAP |
| Supervised Boot Interfaces | ||
| JTAG TAP interface |
Serial TAG test access port controller for boundary scan and AMD opcodes |
– |
| SelectMAP | 8, 16, or 32 bit interface | SelectMAP Boot Mode |
| SBI | Facilitates booting via SelectMAP and JTAG | SBI for JTAG and SelectMAP |
| Flash Memory Interfaces | ||
| OSPI | Octal SPI 8-bit interface | OSPI Flash Boot Mode |
| QSPI | Quad SPI 4-bit and 8-bit interface | QSPI Flash Boot Mode |
| SD | SD v2.0/3.0 compatible interface controller | SD Flash Boot Mode |
| eMMC | eMMC v5.1 with 8-bit interface | – |
| UFS | 8-bit v3.1 universal flash storage interface controller | UFS Host Controller |
| System Monitoring | ||
| PMC SysMon | Voltage and temperature monitor with I2C interface on PMC MIO pins | Versal Adaptive SoC System Monitor Architecture Manual (AM006) |
| PMC ClkMon | Clock monitor | – |
| Security Resources | ||
| Device security | Security management | Security Units |
| AES-GCM/ECB | Security engine for encryption and decryption | PMC AES |
| SHA2 | SHA-256, SHA-384, SHA-512 secure hash algorithms | Secure Hash Algorithms |
| SHA3 | SHA3-256, SHA3-384, SHA3-512, and SHAKE-256 secure hash algorithms (two units) | Secure Hash Algorithms |
| RSA/ECC | Security public-key cryptography engine with authentication algorithms | RSA/ECC |
| TRNG | True random number generator | True Random Number Generator |
| PUF | Physical unclonable function | Physically Unclonable Function |
| BBRAM | Battery-backed RAM and controller | Battery-Backed RAM |
| Timers, Counters, and RTC | ||
| SWDT | System watchdog timer with generic and windowed options for PLM firmware | System Watchdog Timers |
| RTC | Battery backup counter for time keeping | Real-Time Clock |
| I/O Peripheral Controllers | ||
| PMC GPIO | General purpose I/O controller (52 channels) | GPIO Controller |
| PMC I3C0, 1 | I3C controllers with I2C compatibility | I3C Controller |
| Resets and Clocks | ||
| Resets | PMC reset controller | – |
| Clocks | PMC clock controller | – |