The Versal architecture comprises a rich set of adaptable resources. The amount of information required in a PDI to initialize the resources in each Versal adaptive SoC depends on the part number. Because a PDI can also contain user code and data, AMD recommends system architects make an informed estimate of PDI size based on information provided by AMD, together with system-specific insights known by the architect. The following table lists the small contributor elements to the PDI size generated by the Vivado/AMD Vitis™ tools and maximum sizes are provided for estimation purposes.
| PDI Contributor | Maximum Size | Maximum Size (Mbits) |
|---|---|---|
| Boot header 1 | 3,968 Bytes | <<1 |
| PLM ELF 1 | 384 KBytes | 3 |
| PMC CDO 1 | 80 KBytes | <1 |
| Meta header 1 | 16 KBytes | <1 |
| LPD CDO 1,2 | 20 KBytes | <1 |
| FPD CDO 1,2 | 20 KBytes | <1 |
| PSM ELF 1,2 | 256 KBytes | 2 |
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Additional contributor elements to PDI size are generated by the Vivado/Vitis tools, and when present, are significantly large with sizes depending on the Versal adaptive SoC part number.
- Programmable logic (PL) configuration frame interface (CFI) information
- Network on chip (NoC) programming interface (NPI) information
- AI Engine programming information
The following table provides size estimation guidance for the larger contributor elements to the PDI.
| Series | Device | CFI Maximum Size (Mbits) | NPI Maximum Size (Mbits) | AIE Maximum Size (Mbits) | Total (Mbits) |
|---|---|---|---|---|---|
| Versal AI Edge Series Gen 2 | 2VE3304 | 69.0 | 1.0 | 9.2 | 79.2 |
| 2VE3358 | 69.0 | 1.0 | 9.2 | 79.2 | |
| 2VE3504 | 225.8 | 1.9 | 30.7 | 258.5 | |
| 2VE3558 | 225.8 | 1.9 | 30.7 | 258.5 | |
| 2VE3804 | 415.9 | 4.5 | 55.3 | 475.7 | |
| 2VE3858 | 415.9 | 4.5 | 55.3 | 475.7 | |
| Versal Prime Series Gen 2 | 2VM3358 | 69.0 | 1.0 | – | 70.0 |
| 2VM3558 | 225.8 | 1.9 | – | 227.7 | |
| 2VM3654 | 347.3 | 6.5 | – | 353.8 | |
| 2VM3858 | 415.9 | 4.5 | – | 420.4 | |
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User Code/Data (U-Boot, OS Image, Application, File System)
The remaining image contributors to the PDI size are highly dependent on the system design and cannot be known or provided by AMD.
Due to the many factors that can influence the desired storage capacity, AMD recommends system architects model their complete needs using “maximum values” based on information provided in this chapter, coupled with system insight and PDIs generated by the AMD Vivado™ /Vitis tools reflecting actual boot flow options and including user code/data.
The desired storage capacity guides the selection of the most appropriate Versal adaptive SoC boot modes. For those boot modes used with a non-volatile memory device, the desired storage capacity also guides the selection process of this additional component.
Boot modes supporting NAND flash technology (that is, eMMC or SD) provide options for the highest capacity storage, while boot modes supporting NOR flash technology (that is, QSPI or OSPI) provide options for mid-to-low capacity storage (typically 2 Gbit or lower, with 4 Gbit possible using dual stacked/parallel arrangements). For NOR flash technology, the following table provides guidance on minimum flash component size for storing a single non-secure and uncompressed PDI for a primary boot of a Versal adaptive SoC. The effect of user code/data storage, security, compression, partial reconfiguration, or multiple PDI images is a supplemental consideration.
| Series | Device | Minimum Boot Flash Capacity (Mbits) |
|---|---|---|
| Versal AI Edge Series Gen 2 | 2VE3304 | 128 |
| 2VE3358 | 128 | |
| 2VE3504 | 512 | |
| 2VE3558 | 512 | |
| 2VE3804 | 512 | |
| 2VE3858 | 512 | |
| Versal Prime Series Gen 2 | 2VM3358 | 128 |
| 2VM3558 | 256 | |
| 2VM3654 | 512 | |
| 2VM3858 | 512 |