PCIe Resets on MIO Pins - PCIe Resets on MIO Pins

PCIe Resets on MIO Pins - PCIe Resets on MIO Pins - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID

AM026

Release Date

2025-12-23

Revision

1.3 English

The following table includes the PCIe reset signals routed from the MIO pins to the PCIe controllers (device options). The reset pins are shown in the tables of the MIO-at-a-Glance Tables section.

Table 1. PCIe Controller Reset Input Signals
Signal Name	I/O	MIO-at-a-Glance Table	Notes
PCIE0_RESET_b	Input	RST0	Reset to PCIe controller 0
PCIE1_RESET_b	Input	RST1	Reset to PCIe controller 1