The buffer output include drive strength, slew rate controls, and output enable.
Drive Strength
The output drive strength is controlled by two bits per output using a bit from a drive 0 register and a bit from a drive 1 register to select 4, 8, and 12 mA drive strength for each individual MIO pin.
- 00: reserved
- 01: 4 mA
- 10: 8 mA (reset default)
- 11: 12 mA
Slew Rate
Select between slow (0) and fast (1).
Output Enable
The output enable for each multiplexed I/O buffer is normally controlled by the peripheral controller. There are tristate override registers that can be used to disable an entire bank of signals, if needed.
When the tristate override control bit equals 1, the output on the I/O buffer is disabled and the pin will float according to the weak pull-up or pull-down settings.
MIO Output Buffer Control Registers
The MIO output controls are summarized in the following table.
| Feature | PMC_IOP_SLCR Registers | LPD_IOP_SLCR Registers | Description | |
|---|---|---|---|---|
| PMC MIO Bank 0 | PMC MIO Bank 1 | PS LPD MIO Bank 2 | ||
| Pins 0 to 25 | Pins 26 to 51 | Pins 0 to 25 | ||
|
Drive strength |
MIO_Bank0_Drv0_Sel |
MIO_Bank1_Drv0_Sel |
MIO_Bank2_Drv0_Sel |
drv1 | drv0: |
| Slew | MIO_Bank0_Slew_Sel | MIO_Bank1_Slew_Sel | MIO_Bank2_Slew_Sel |
0: Slow-slew |
| Tristate override | MIO_Bank0_Tristate | MIO_Bank1_Tristate | MIO_Bank2_Tristate |
0: Output enable is controlled by the peripheral |