Network On Chip - Network On Chip - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The TRM introduces the network on chip (NoC) interconnect and includes it in high-level subsystem block diagrams, but does not explain its implementation or behavior.

Configuration

The NoC is configured using the AMD Vivado™ IP integrator. Configuration data is written to the NoC units via the NPI programming interface.