MIO Routing Considerations - MIO Routing Considerations - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English
Note: There are several important MIO pin assignment considerations. The MIO-at-a-Glance tables and the I/O pin assignment considerations are helpful for pin planning. Each I/O peripheral chapter includes individual MIO signal tables for each controller/unit that uses the MIO pins. The MIO-at-a-Glance table includes links to these individual MIO signal tables.

I/O Interface Group

I/O interfaces include bus protocol signals with timing specifications and signals without timing requirements. The signals with timing requirements must be routed to the device pins as a group. The MIO pin groupings are shown in the individual MIO tables in the I/O peripheral chapters.

The pin groupings are shown in the columns of the individual MIO signal tables in various chapters. Select one table column of pin assignments for the timing-sensitive signals, and do not mix and match column entries.

For I/O signals without a timing specification (for example, write protect, card detect, etc.), their own individual pinout routing can be used.

Peripheral Interface Frequencies

The clocking frequency for a peripheral interface usually depends on the device speed grade. Nominal interface frequencies are usually included in the associated chapter. The I/O timing specifications are provided in the data sheet.

Boot Device Selection

The boot device options are shaded in the PMC MIO Pin Tables and are listed in the Boot Modes and Interfaces chapter.