Each MIO pin buffer has several register controls:
- Internal pull-up and pull-down
- Schmitt trigger input enable
- Output enable
- Output drive strength and slew rate
The characteristics of the MIO pins are individually controlled:
- PMC MIO pins 0 to 25: PMC_GPIO Module register, bank 0
- PMC MIO pins 26 to 51: PMC_GPIO Module register, bank 1
- PS LPD MIO pins 0 to 25: LPD_IOP_SLCR registers, bank 2