The I/O interfaces for the IOP controllers and other units are routed to the PMC and LPD MIO multiplexers. Some signals can be routed to the EMIO interface to the PL. Some IOP interfaces and signals are only available on the MIO (for example, quad SPI). Other I/O signals are only available on the EMIO interface (for example, LPD DMA handshake control).
The routing is configured by the registers in the PMC_IOP_SLCR and LPD_IOP_SLCR and register sets. The interfaces and signals that are routed through the MIO-EMIO are listed in the following table with their I/O interface routing options.
| Interface or Signal | Controller Location | Access | Notes | ||
|---|---|---|---|---|---|
| PMC MIO | LPD MIO | EMIO | |||
|
CAN_FD0 |
LPD | Yes | Yes | Yes | |
|
GEM0 |
LPD | Yes | Yes | – | RGMII |
| – | – | Yes | GMII/MII, TSU, and external FIFO | ||
| Yes | Yes | Yes | MDIO | ||
| LPD DMA | LPD | – | – | Yes | Flow control |
| PMC_GPIO | PMC | Yes | – | – | PMC GPIO Banks 0, 1 (no bank 2) |
| – | – | Yes | PMC GPIO Banks 3, 4 | ||
| LPD_GPIO | LPD | – | Yes | – | LPD GPIO Bank 0 (no banks 1, 2) |
| – | – | Yes | LPD GPIO Bank 3 | ||
|
LPD_I3C0 |
LPD | Yes | Yes | Yes | |
| LPD_I3C2:7 | LPD | – | – | Yes | |
| SYSMON_I2C | PMC | Yes | Yes | Yes | |
| Octal SPI | PMC | Yes | – | ||
| SelectMAP | PMC | Yes | – | – | |
|
SPI0 |
LPD | Yes | Yes | Yes | |
| Quad SPI | PMC | Yes | – | – | |
| CoreSight™ Trace Out | FPD | 16-bit | 16-bit | 32-bit | |
|
TTC0 |
LPD | Yes | Yes | Yes | Clock in and wave out |
|
TTC4 |
LPD | ||||
|
UART0 |
LPD | Yes | Yes | Yes | MIO only includes RX, TX, CTS, and RTS |
| USF | PMC | Yes | - | - | Includes GTs for I/O |
| USB_2.0 | LPD | Yes | – | – | ULPI PHY interface |
| RPU_A_SWDT | LPD | Yes | – | Yes | Interrupt signal only (INT) |