MDB5,10G Ethernet MAC and Aurora HSDP - MDB5,10G Ethernet MAC and Aurora HSDP - AM026

Introduction

Within the High Speed Connectivity peripherals is the PCIe/10G/HSDP unit. Inside the unit, one PS-GTYP PHY is shared between the two PCIe cores (PCIe0, PCIe1), one 10G Ethernet MAC (10GbE) controller and one Aurora HSDP port. There exists a PIPE mux logic module that is responsible for handling the data and clock muxing between the PHY and the IP blocks. It also provides support logic for the PCIe/10GbE inter-core lookback feature as well as a functional test of PS-GTYP via the PL.

Refer to the following figure for the PCIe/10GbE subsystem block diagram.

The following table describes the valid set of configurations to map the PS-GTYP lanes to the IP blocks.