LPD MIO Pin Table - LPD MIO Pin Table - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The following table lists the LPD MIO pin assignments.

Table 1. LPD MIO Pin Assignments (Bank 502)
Pins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
LPD Controllers
CANFD TX 1 RX 1 RX 0 TX 0 RX 3 TX 3 RX 2 TX 2 TX 1 RX 1 RX 0 TX 0 RX 3 TX 3 RX 2 TX 2 TX 1 RX 1 RX 0 TX 0 TX 1 RX 1 RX 0 TX 0 TX 1 RX 1
GEM 0 RGMII TX CLK TXD 0 TXD 1 TXD 2 TXD 3 TX CTL RX CLK RXD 0 RXD 1 RXD 2 RXD 3 RX CTL
GEM 1 RGMII TX CLK TXD 0 TXD 1 TXD 2 TXD 3 TX CTL RX CLK RXD 0 RXD 1 RXD 2 RXD 3 RX CTL
GEM n MDIO - - - - CLK 1 DATA 1 CLK 0 DATA 0
GEM TSU CLK CLK
PCIE RST 0 RST 1
LPD GPIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
LPD I3C 0 SCL SDA SCL SDA
LPD I3C 1 SCL SDA SCL SDA SCL SDA
MMI HDP HDP
SPI0 SCLK CS2 CS1 CS0 MISO MOSI SCLK CS2 CS1 CS0 MISO MOSI
SPI1 SCLK CS2 CS1 CS0 MISO MOSI SCLK CS2 CS1 CS0 MISO MOSI
SysMon I2C/SMB SCL SDA SMB SCL SDA SMB SCL SDA SMB SCL SDA SMB SCL SDA SMB SCL SDA SMB
TRACE CTL D 0 D 1 D 2 CLK D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15
TTC n

CLK 1

WA 1

CLK 0

WA  0

CLK 2

WA 2

CLK 1

WA 1

CLK 0

WA 0

CLK 1

WA 1

CLK 0

WA 0

UART 0 RXD TXD CTS RTS RXD TXD CTS RTS RXD TXD CTS RTS
UART 1 TXD RXD CTS RTS TXD RXD CTS RTS TXD RXD CTS RTS