LPD DMA Implementations - LPD DMA Implementations - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The descriptor-driven, general purpose DMA unit versions are compared in the following table.

Table 1. LPD DMA Implementations
Device Generation Instances DMA Core Design Buffer Flow Control Interface
UltraScale+ MPSoC LPD and FPD AMD IP, version 1.0 LPD: 2 KB

FPD: 4 KB

DMA2PL_CACK
Versal device LPD AMD IP 4 KB New DMA2PL_CACK flow control signal behavior
Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 LPD x2 AMD IP 4 KB  
In Versal devices, the PL must not use DMA2PL_CACK in combinational logic to generate PL2DMA_CVLD because it can result in unpredictable operation. The signal is shown in PL Flow-Control Interface.
Note: There are two identical DMA units; one is also known as ADMA and the other as SDMA.