Clocks
Each controller receives its own reference clock I3Cx_REF_CLK that must be set to 160 MHz. The controller also includes an APB programming interface clock.
Resets
Each controller has one reset state that is entered when the device is locally reset by the SW_Reset register, or by a software reset that includes the LPD, or a POR reset.
System Interrupt
Each I3C controller generates an active-High, level-sensitive system interrupt based events and programming of the I3C interrupt mask register. These IRQ numbers are included in the device-level system interrupts table in the System Interrupts chapter.
- PMC_I3C_IRQ
- LPD_I3C0_IRQ
- LPD_I3C1_IRQ
System Error
The controller does not generate a system error.
I/O Interface
The options for routing the I3C two wire I/O interface include the LPD MIO pins, the PMC MIO pins, and the PL EMIO. The options are shown in the MIO-at-a-Glance Tables section.