The four controllers in the SoC include:
- Two LPD I3C controllers with I2C fast mode plus, 100 MHz (routed to PMC and LPD MIO pins)
- Six LPD I3C controllers with I2C fast mode plus, 100 MHz (EMIO)
- One PMC I3C controller with I2C fast mode plus, 100 MHz (dedicated I/O pins for DDR DIMM control)
- One PMC SYSMON I2C controller, 400 MHz (multiplexed on PMC and LPD MIO pins)
The following table summarizes the I3C controller configuration options.
| Option | Setting | Notes |
|---|---|---|
| Role | Secondary manager | Switchable mode between current to non-current manager |
| Basic | HDR-DDR supported | Does not support HDR-TS |
| Buffer sizes |
Commands: 4 |
No DMA handshaking interface |
| Manager mode configuration |
Addressable devices: 11 |
Device reset support in IBHR pattern settings |
| Manager |
IBI status: 8 |
Typical |
| Slave configuration | IBI support | |
| Slave maximum data speed | Programmable maximum Read and write (tSCO) | |
| Clock period configuration | Core clock period: 5 |