I2C and I3C Controller Implementations - I2C and I3C Controller Implementations - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

I3C Controller Note

The Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices have eight I3C controllers in the LPD and one I3C controller in the PMC. Each controller has an I2C core and an I3C core that shares the same APB programming interface, reference clock, and I/O signal pins. In I2C mode, they support the fast mode plus I/O clocking frequency of 100 MHz. There is no change to the SYSMON I2C controller. Its maximum I/O interface frequency remains at 400 kHz.

The Versal device I2C controllers are similar to the controllers in the AMD Zynq™ UltraScale+™ MPSoCs I2C controllers. The following table shows the I2C and I3C controller instances and implementations.

Table 1. I2C and I3C Controller Implementations
Device Generation Instances I2C Controller I3C Controller
UltraScale+ MPSoC 1x I2C in PMC SYSMON

2x I2C in LPD

Cadence dcw0701_R114_f0100_final Not available
Versal adaptive SoC 1x I2C in PMC on MIO pins

2x I2C in LPD on MIO pins

1x I2C PMC SYSMON on MIO pins

Cadence dcw0701_R114_f0100_final Data_hold_control register added to extend SDA output hold time Not available
Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices 1x I3C in PMC on MIO pins

2x I3C in LPD on MIO pins

6x I3C in LPD on EMIO pins

I2C core is integrated in the I3C controller Synopsys 1.01a-lca00