The following sections describe the I2C programming model.
Programming Interface
The controllers includes a simple memory-mapped APB programming interface for software:
- Control and status registers
- Transmit data register port
- Receive data register port
Controller Reset
- LPD I3C controller 0 is reset by the CRL.RST_I3C0 register
- LPD I3C controller 1 is reset by the CRL.RST_I3C1 register
- PMC I3C controller is reset by the CRP.RST_I3C register
The [RESET] bits are toggled by software:
- 0: Run mode
- 1: Reset state
I/O Signals
The SCL and SDA signals can be routed to one of many sets of MIO pins or to the PL EMIO port signal interface by default.
The MIO signals are first routed to either the PMC or LPD MIO banks using select register bits:
Use the IOP_SLCR.LPD_MIO_SEL [I3Cx] register bit to select between the PMC and LPD MIO pin multiplexers.
The signal for each MIO pin is configured using SLCR MIO_PIN_xx registers:
- PMC_SLCR register module MIO_PIN_0 through MIO_PIN_51
- LPD_SLCR register module, MIO_PIN_0 through MIO_PIN_25
The MIO programming is described in the Multiplexed I/O Signal Pins section.
If a MIO PIN register does not map an I3C I/O pin, then the signal is available as an EMIO port interface signal. The SLCR registers also configure the MIO pin buffer input and output characteristics. The I3C I/O signals are listed in I/O Interface Signals.
Reference Clock
Clocks are generated by the PMC and LPD clock controllers.
The reference clock is used for the controller logic, registers, and memories. It is also an input to the baud rate generator. Each controller has its own reference clock that comes from the PMC or LPD clock generator. Each register includes the three fields [SRCSEL], [DIVISOR], and [CLKACT].
Control Registers
- PMC_I3C_REF_CLK controlled by the CRP I3C_REF_CTRL register
- LPD_I3C0_REF_CLK controlled by the CRL I3C0_REF_CTRL register
- LPD_I3C1_REF_CLK controlled by the CRL I3C1_REF_CTRL register