I2C Modes - I2C Modes - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English
Note: In a system where multiple managers are running with the same clock frequency, the controller will arbitrate properly. This includes standard, fast, and fast plus. Arbitration is not supported when initiating frames at different bus frequencies.

Basic Manager Mode

The manager is always the device that drives the SCL clock signal. The attached devices respond to the controller. There can be multiple attached responders on the I2C bus; however, there is normally only one manager. To select manager mode, set LPD_I2C.CTRL [MS] bit = 1.

It is possible to have multiple managers attached to the bus.

Multi-Manager Mode

Multi-manager mode arbitrates bus speed and detect clashes. To select manager mode, set LPD_I2C.CTRL [MS] bit = 1.

Bus Monitoring Manager Mode

The monitoring option is enabled by setting CTRL [SLVMON] bit = 1. To monitor a specific device, wait until the ACK is received or a timeout occurs.

I2C Response Mode

In managerial response mode, the controller responds to other managers on the bus. To configure the mode of the controller, program the CTRL [MS] bit.

The controller receives the SCL from another attached manager and responds to its assigned address.

I2C Glitch Filter

The digital glitch filter is applied to the SDA and SCL inputs. This filter removes transients that occur on the inputs so the controller can see the intended input signal level.

The filter logic is clocked by the APB programming interface clock (xxx_LSBUS_CLK). This clock is normally 100 MHz (10 ns).

In this case, the glitch filter is set to 50 ns by the reset default value. The length of filtering time is set by the GLITCH_CTRL [GF] bit field.

If the glitch filter control is set to 0, then the glitch filter is disabled.

Note: The glitch filter duration must not exceed 50 ns. The filter is controlled by the Glitch_Filter register and clocked by the PMC_LSBUS clock. For a 150 MHz LSBUS clock frequency, the Glitch_Filter register should be set to a value of 5 to provide a 33.3 ns filter duration.

Loopback Test

In loopback mode, the serial clocks are connected together and the serial data signals are connected together.

Note: The loopback test is available for I2C. Loopback test is not available for I3C in 2VE3804, 2VE3558, 2VE3858, and 2VM3858 devices.