For clock frequencies greater than 25 MHz, the DLL generates the DLL_IO_CLK for the SCLK output and the DLL_RX_CLK for the RX interface to latch the data input signals.
The timing of the DLL_RX_CLK relative to the DLL_IO_CLK reference clock is adjusted using a 180-tap unit. The RX tap is selected by the SD_eMMC ITAP_DLY [sel] bit field. The clock frequency determines the number of useful taps.
- 200 MHz: 30 taps
- 100 MHz: 60 taps
- 50 MHz: 120 taps
- 33 MHz: 180 taps
Example programming values are shown in DLL Programming Example.