GPIO Controller Implementations - GPIO Controller Implementations

GPIO Controller Implementations - GPIO Controller Implementations - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID

AM026

Release Date

2025-12-23

Revision

1.3 English

The functionality of the GPIO controller implementations are the same for all devices.

Table 1. GPIO Controller Implementations
Device Generation	MIO Pin Drive Strength	PMC	LPD
AMD UltraScale+™ MPSoC	2, 4, 8, and 12 mA	Platform management unit (PMU) in LPD: 3x MIO banks (78 channels) 3x EMIO banks (78 channels)
AMD Versal™ adaptive SoC	4, 8, and 12 mA	IOP GPIO controller: 2x MIO banks (52 channels) 2x EMIO banks (64 channels)	IOP GPIO controller: 1x MIO bank (26 channels) 1x EMIO bank (32 channels)
Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2	4, 8, and 12 mA	IOP GPIO controller: 2x MIO banks (52 channels) 2x EMIO banks (64 channels)	IOP GPIO controller: 1x MIO bank (26 channels) 1x EMIO bank (32 channels)