The following table lists the FPD SMMU and coherent implementations.
| Device Generation | System MMU | FPD Coherent Interconnect |
|---|---|---|
| UltraScale+ MPSoC | SMMU-500 is in both the Zynq UltraScale+ MPSoC and the Versal adaptive SoC | ACP, ACE |
| Versal adaptive SoC |
Arm SMMU-500 TCU version is r2p4 TBU version is r2p1 |
Cache coherent interconnect, CCI-500 with
single L2-cache Version PL422-r1p0-00rel0 |
| Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 |