Introduction
The Display Controller (DC) is positioned between the DisplayPort (DP) TX 1.4 controller and PL. The main function of the DC is to fetch video/graphics and related audio data from memory and/or PL and send the combined video stream to the video DisplayPort. It is connected to the PSXC via a 128b AXI-MM bus. It will also provide DMA support for frame-buffer accesses from/to DDR. It can also send/receive stream data to/from the PL interface in each direction. In addition, the DC will be capable of performing several video processing functions including blending, chroma sub-sampling, and color space conversion.
The DC has a bypass mode to passthrough from one 8kp30 stream up to four independent 4kp30 streams from the PL directly to the DP TX controller. The DP IP supports up to 4 streams (MST mode). Each stream timing and resolution can be independent. When only one video stream is selected, it can support a multi-pixel mode (single, dual or quad pixel mode).
When the DC is bypassed, the DP TX can receive from the PL
- 1 8kp30 stream (on one of the 4 stream interfaces in quad pixel mode running at 300MHz)
- 1 4kp120 stream (on one of the 4 stream interfaces in quad pixel mode running at 300MHz)
- 2 independent 4kp60 streams
- 4 independent 4kp30 streams
Refer to the following figure for the DC top-level block diagram:
The key blocks in the DC subsystem are:
- Video pipeline
- DMA controller
- Channel buffers
- Hardware cursor
- Control registers
A detailed description of the blocks is given in the next section.: