Refer to the following figure for the display controller clock sources in:
Figure 1. Display Controller Clock Sources
The clocks used in the Display Controller are summarized in the following table:
| Clock | Clock Name | Source | Description |
|---|---|---|---|
| PIXEL_CLK |
pl_mmi_dc_1x_clk pl_mmi_dc_2x_clk pl_mmi_dc_S0_clk pl_mmi_dc_S1_clk pl_mmi_dc_S2_clk pl_mmi_dc_S3_clk |
PL/PSX/MMI | Video timing generation and video processing. When the PL is available,
the clock is input from the PL. Otherwise, the clock needs to come from
MMI or PS. DC video pipeline operates at Pl_mmi_dc_2x_clk. Whereas, PL
IPs operate at divide by two of 2x clock (i.e., pl_mmi_dc_1x_clk).
pl_mmi_dc_S*_clk are the respective individual video stream clocks used
in bypass mode. To meet the maximum skew requirement between pl_mmi_dc_2x_clk and pl_mmi_dc_1x_clk, the two clocks must be generated from the same MBUFGCE. See the Processing System Wizard v1.0 LogiCORE IP Product Guide (PG450) MMI peripherals section for more information. |
| AUDIO_CLK |
pl_mmi_i2s_s0_clk pl_mmi_i2s_s1_clk pl_mmi_i2s_s2_clk pl_mmi_i2s_s3_clk |
PL/PSX/MMI | Audio timing generation and audio processing. When the PL is available, the clock is input from the PL. Otherwise, the clock needs to come from MMI or PS. pl_mmi_i2s_S*_clk are the respective individual audio stream clocks used in bypass mode. |
| SDP_CLK | pl_mmi_dc_1x_clk | PL/PSX/MMI | SDP data forwarding to DP. When the PL is available, the clock is input from the PL. Otherwise, the clock needs to come from MMI or PS. |
| DMA_CLK | dc_apb_clk | PSX/AXI | AXI transactions. |
| STC_CLK | mmi_27m_dig_clk | The system time clock is based on a 27 MHz reference clock and a 42-bit counter. |