DMA - DMA - AM026

DMA Endianism

The default configuration of the DMA is to use little endian format. And may be programmed to swap the endianism using bits 6 and 7 of the DMA configuration register (0x0010). Bit 6 controls the endianism of the management operations and bit 7 controls the endianism of the data operations.

DMA Transactions

The DMA uses separate transmit and receive lists of buffer descriptors, with each descriptor describing a buffer area in memory. This can allow Ethernet packets to be broken up and scattered around the system memory (multi-buffer operation), although one buffer per frame is also permitted. The arbitration scheme that is deployed in GEM is least-recently-granted and fixed priority.

Transfer size can be programmed to be 32, 64, or 128-bit words using the DMA bus width select bits in the network configuration register and burst size may be programmed to single access or bursts of 4, 8, 16, or 256 words using the DMA configuration register. 256-word bursts are not supported with an AXI3 interface. The DMA adheres to AXI4 specification of not exceeding 4 KB address boundary per transaction. If occurs, the DMA will separate out into two bursts. The maximum length for a jumbo frame is 16,320 bytes due to the limitation in the length field of the DMA descriptor.

When the DMA is configured to use SRAM-based packet buffers, it can be programmed into a low-latency mode, known as partial store and forward. Enabled via the TX and RX partial store and forward programmable registers. When the transmit partial store and forward mode is activated, the transmitter will only begin to forward the packet to the MAC when there is enough packet data stored in the packet buffer. Similarly, when the receive partial store and forward mode is activated, the receiver will only begin to forward the packet to the external AXI slave when enough packet data is stored in the packet buffer.

Receive DMA Buffers

Received frames, optionally including FCS, are written to receive buffers stored in AXI memory. The start location for each receive buffer is stored in memory in a list of receive buffer descriptors at an address location pointed to by the receive buffer queue pointer. The base address for the receive buffer queue pointer is configured in software using the receive buffer queue base address register(s).

The number of words in each buffer descriptor (BD) is dependent on the operating mode. Each BD word is defined as 32-bits. The first two words (word 0 and word 1) are used for all BD modes.

In extended buffer descriptor modes (DMA configuration register bit 28 = 1), two buffer descriptor words are added for 64-bit addressing mode and two buffer descriptor words are added for time-stamp capture. Therefore, there are either two, four, or six buffer descriptor words in each buffer descriptor entry depending on operating mode, and every buffer descriptor entry has the same number of words.

• Every descriptor is 64-bits wide when 64-bit addressing is disabled and the descriptor time-stamp capture mode is disabled.
• Every descriptor is 128-bits wide when 64-bit addressing is enabled and the descriptor time-stamp capture mode is disabled.
• Every descriptor is 128-bits wide when 64-bit addressing is disabled and the descriptor time-stamp capture mode is enabled.
• Every descriptor is 192-bits wide when 64-bit addressing is enabled and the descriptor time-stamp capture mode is enabled.

When Descriptor Timestamp Capture mode is enabled, the table below identifies the added descriptor words:

Transmit DMA Buffers

Frames to transmit are stored in one or more transmit AXI buffers. Zero length AXI buffers are allowed, and the maximum number of buffers permitted for each transmit frame is 128.

The start location for each transmit buffer is stored in AXI memory in a list of transmit buffer descriptors at a location pointed to by the transmit buffer queue pointer. The base address for this queue pointer is set in software using the transmit buffer queue base address register(s).

The number of words in each buffer descriptor depends on the operating mode. The first two words (word 0 and word 1) are used for all buffer descriptor modes. In extended buffer descriptor mode, two buffer descriptor words are added for 64-bit addressing mode and two buffer descriptor words are added for timestamp capture. Therefore, there are either two, four, or six buffer descriptor words in each buffer descriptor entry depending on operating mode, and every buffer descriptor entry has the same number of words.

In transmit Extended Buffer Descriptor Modes (bit 29 in the DMA configuration register), two BD words are added for 64 bit addressing mode and two BD words are added for timestamp capture. There are therefore either two, four or six BD words in each BD entry depending on operating mode, and every BD entry will have the same number of words.

MAC Loopback

Note: Receive and transmit must be disabled when making the switch into and out of internal loopback because the clocks provided might glitch while switching to the loopback reference clock

Link Status

An interrupt is generated each time the PCS link status changes (i.e. link good or link bad).

Copy All Frames (or Promiscuous Mode)

If the copy all frames bit is set in the network configuration register, then all frames (except those that are too long, too short, have FCS errors, or have rx_er asserted during reception) are copied to memory. Frames with FCS errors are copied if bit [26] is set in the network configuration register.

Display Copy of Pause Frames

Pause frames can be prevented from being written to memory by setting the disable copying of pause frames control bit [23] in the network configuration register. When set, pause frames are not copied to memory regardless of the copy all frames bit, whether a hash match is found, a type ID match is identified, or if a destination address match is found.

Broadcast Address

Frames with the broadcast address of 0xFFFFFFFFFFFF are stored to memory only if the no broadcast bit in the network configuration register is set to zero.

Hash Addressing

The hash address register is 64-bits long and takes up two locations in the memory map. The least significant bits are stored in hash register bottom and the most significant bits in hash register top.

• The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames

The destination address is reduced to a 6-bit index into the 6- bit hash register using the

following hash function. The hash function is an XOR of every sixth bit of the destination address

hash_index[05] = da[05] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]

hash_index[04] = da[04] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]

hash_index[03] = da[03] ^ da[09] ^ da[15] ^ da[21] ^ da[27]^ da[33] ^ da[39] ^ da[45]

hash_index[02] = da[02] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]

hash_index[01] = da[01] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]

hash_index[00] = da[00] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]

Wake-on-Lan Support

If one of these events occurs, WOL detection is indicated by asserting the wake-up interrupt. These events can be individually enabled through bits[19:16] of the wake-on-LAN register. Also, for WOL detection to occur, the receive enable must be set in the network control register.

The wake-up interrupt is asserted due to multicast filter events, an ARP request, or a specific address 1 match even in the presence of a frame error. For magic-packet events, the frame must be correctly formed and error free.

The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame. The reserved value of 0x0000 for the Wake-on-LAN target address value will not cause an ARP request event, even if matched by the frame

VLAN Support

The VLAN tag is inserted at the 13th byte of the frame adding an extra four bytes to the frame. To support these extra four bytes, the 10GbE controller can accept frame lengths up to 1,536 bytes by setting bit [8] in the network configuration register. If the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame.

10GbE can be configured to reject all frames except VLAN tagged frames by setting the discard non-VLAN frames bit in the network configuration register.

The 10GbE decoder treats a VLAN tag with the CFI bit set to one as invalid. Packet inspection does not continue past the source address if a VLAN tagged frame with the CFI bit set to one is received. CFI stands for canonical format indicator and was defined to be zero for Ethernet frames. A value of one was used for VLAN token ring frames. 802.1Q has since redefined this bit to mean drop eligible indicator (DEI). For backward comparability reasons 10GbE continues to treat VLAN tagged frames with the CFI/DEI bit set as invalid.

Checksum Offload for IP, TCP, and UDP

10GbE can be programmed to perform IP, TCP, and UDP checksum offloading in both the receive and transmit direction which is enabled by setting:

Bit 24 in the network configuration register for receive and

For IP, TCP, or UDP checksum offload to be useful, the operating system containing the protocol stack must be aware that this offload is available so that it can make use of the fact that the hardware can either generate or verify the checksum.

Receiver Checksum Offload

When an IP, TCP, or UDP frame is received, the receive buffer descriptor gives an indication if 10GbE was able to verify the checksums. There is also an indication if the frame had SNAP encapsulation. These indication bits will replace the type ID match indication bits when the receive checksum offload is enabled. If any of the checksums are verified incorrect by 10GbE, the packet is discarded and the appropriate statistics counter incremented.

Transmitter Checksum Offload

The transmitter checksum offload is only available if 10GbE is configured to use the DMA in packet buffer mode and full store and forward mode is enabled. This is because the complete frame to be transmitted must be read into the packet buffer memory before the checksum can be calculated and written back into the headers at the beginning of the frame.

If the transmitter checksum engine is prevented from generating the relevant checksums, bits [22:20] of the transmitter DMA writeback status will be updated to identify the reason for the error. Note: The frame will still be transmitted but without the checksum substitution, as typically the reason that the substitution did not occur was that the protocol was not recognized

Receive Header/Data Splitting

The DMA design has support for various optional offload features to reduce CPU overhead.

• Receive header data splitting is a feature which when enabled will force the receive DMA to split a received frame into its header and payload constituent parts.
• The header is not dropped, but instead separated from the payload and placed into its own DMA receive buffer. For example, a TCP/IPv4 frame will be split such that its Ethernet, IPv4 and TCP header is written into one or more buffers, and the TCP payload is written into one or more separate buffers.
• A status bit in the receive descriptors will identify whether the descriptor is pointing to a header buffer or a payload buffer
• Another status bit will identify whether the descriptor is pointing to the last buffer of a header (the header may be split over multiple buffers).
• The length of the header will also be written in the descriptor that points to the last buffer of the header.

When header/data splitting is enabled, ALL received frames will have their L2/L3/L4 headers separated. Note: Even standard Ethernet only frames containing just 14 bytes of header will be separated. Bit 5 of the DMA configuration register at offset 0x10 enables/disables header data splitting.

If any of these encapsulations are recognized, then they will be included in the header buffer.

Low Power Features

10GbE provides Energy-Efficient Ethernet (EEE) support. IEEE 802.3az adds support for energy efficiency to Ethernet. These are the key features of 802.3az:

• Allows a system’s transmit path to enter a low power mode if there is nothing to transmit
• Allows a PHY to detect whether its link partner’s transmit path is in low-power mode, therefore allowing the system’s receive path to enter low-power mode
• Link remains up during lower power mode and no frames are dropped
• Asymmetric, one direction can be in low-power mode while the other is transmitting normally
• LPI (Low Power Idle) signaling is used to control entry and exit to and from low power modes
• LPI signaling can only take place if both sides have indicated support for it through auto-negotiation

LPI Operation in IP

It is best to use firmware to control LPI. LPI operation is something that happens at the system level. Firmware gives maximum control and flexibility of operation. LPI operation is straightforward, and firmware should be capable of responding within the required timeframes.

The LPI bit is ORed into the transmit pause functionality so transmission will pause

In other words 8 tx_clk periods. So for example, if sys_wake_time is set to 8 in 100M mode, transmission will be

paused for 8 * 320 ns = 25.6 microseconds after deassertion of tx_lpi_en.